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    METHOD FOR STRUCTURAL LAYER FABRICATION IN MICROMECHANICAL DEVICES
    112.
    发明公开
    METHOD FOR STRUCTURAL LAYER FABRICATION IN MICROMECHANICAL DEVICES 审中-公开

    公开(公告)号：US20230192480A1

    公开(公告)日：2023-06-22

    申请号：US18066755

    申请日：2022-12-15

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Altti TORKKELI ,  Hidetoshi FUJII

    IPC: B81C1/00 ,  B81B3/00

    CPC classification number: B81C1/00968 ,  B81B3/001 ,  B81C2201/0133 ,  B81C2201/0178

    Abstract: A method for manufacturing a structural layer in a silicon wafer is provide. The silicon wafer has at least two areas vertically recessed to at least two recess depths, with the first recess depth being greater than the second recess depth. The method includes forming a silicon dioxide pattern, a mask layer and a silicon dioxide pad layer, etching the structural layer in a main LOCOS oxidation process, and removing the formed layers exposing the recessed structural layer. The manufactured structural layer has a bump structure with the recess depth smaller than the second recess depth, and the recessed area has no edge steps.

    HIGH ASPECT RATIO MEMS DEVICES AND METHODS FOR FORMING THE SAME
    117.
    发明申请
    HIGH ASPECT RATIO MEMS DEVICES AND METHODS FOR FORMING THE SAME 有权
    高比例MEMS器件及其形成方法

    公开(公告)号：US20130230939A1

    公开(公告)日：2013-09-05

    申请号：US13412257

    申请日：2012-03-05

    Applicant: Te-Hao LEE

    Inventor： Te-Hao LEE

    IPC: H01L21/02

    CPC classification number: B81C1/00619 ,  B81C2201/0122 ,  B81C2201/0178

    Abstract: An HF vapor etch etches high aspect ratio openings to form MEMS devices and other tightly-packed semiconductor devices with 0.2 μm air gaps between structures. The HF vapor etch etches oxide plugs and gaps with void portions and oxide liner portions and further etches oxide layers that are buried beneath silicon and other structures and is ideally suited to release cantilevers and other MEMS devices. The HF vapor etches at room temperature and atmospheric pressure in one embodiment. A process sequence is provided that forms MEMS devices including cantilevers and lateral, in-plane electrodes that are stationary and vibration resistant.

    Abstract translation: HF蒸汽蚀刻蚀刻高纵横比开口以形成MEMS器件和其他紧密堆积的半导体器件，其中在结构之间具有0.2μm的气隙。 HF蒸汽蚀刻蚀刻具有空隙部分和氧化物衬垫部分的氧化物塞和间隙，并进一步蚀刻氧化物层，其被埋在硅和其它结构之下，并且理想地适合于释放悬臂和其它MEMS器件。 在一个实施方案中，HF蒸气在室温和大气压下蚀刻。 提供了一种形成MEMS器件的工艺顺序，其包括静止和抗振动的悬臂和侧向平面内的电极。

    Method of making a thick microstructural oxide layer
    118.
    发明授权
    Method of making a thick microstructural oxide layer 失效
    制造厚的微结构氧化物层的方法

    公开(公告)号：US06962831B2

    公开(公告)日：2005-11-08

    申请号：US10342949

    申请日：2003-01-15

    Applicant: Khalil Najafi ,  Chunbo Zhang

    Inventor： Khalil Najafi ,  Chunbo Zhang

    IPC: B81C1/00 ,  H01L21/762 ,  H01L21/66

    CPC classification number: F28F13/185 ,  B81B2203/033 ,  B81C1/0038 ,  B81C2201/0132 ,  B81C2201/0178 ,  F28F2260/00 ,  H01L21/76208

    Abstract: A method of fabricating a thick silicon dioxide layer without the need for long deposition or oxidation and a device having such a layer are provided. Deep reactive ion etching (DRIE) is used to create high-aspect ratio openings or trenches and microstructures or silicon pillars, which are then oxidized and/or refilled with LPCVD oxide or other deposited silicon oxide films to create layers as thick as the DRIE etched depth allows. Thickness in the range of 10-100 μm have been achieved. Periodic stiffeners perpendicular to the direction of the trenches are used to provide support for the pillars during oxidation. The resulting SiO2 layer is impermeable and can sustain large pressure difference. Thermal tests show that such thick silicon dioxide diaphragms or layers can effectively thermally isolate heated structures from neighboring structures and devices within a distance of hundred of microns. Such SiO2 diaphragms or layers of thickness 50-60 μm can sustain an extrinsic shear stress up to 3-5 Mpa. These thick insulating microstructures or layers can be used in thermal, mechanical, fluidic, optical, and bio microsystems.

    Abstract translation: 提供了制造厚二氧化硅层而不需要长时间沉积或氧化的方法和具有这种层的器件。 深反应离子蚀刻（DRIE）用于产生高纵横比的开口或沟槽和微结构或硅柱，然后用LPCVD氧化物或其他沉积的氧化硅膜氧化和/或再填充以产生与DRIE蚀刻的厚度相同的层 深度允许。 已达到10-100mam范围内的厚度。 垂直于沟槽方向的周期性加强筋用于在氧化过程中为支柱提供支撑。 所得的SiO 2层是不渗透的并且可以承受较大的压力差。 热测试表明，这种厚的二氧化硅隔膜或层可以有效地将加热的结构与邻近的结构和器件隔离在一百微米的距离内。 厚度为50-60μm的这种SiO 2膜或层可承受高达3-5Mpa的外在剪切应力。 这些厚的绝缘微结构或层可用于热，机械，流体，光学和生物微系统。

    Insulating micro-structure and method of manufacturing same
    119.
    发明授权
    Insulating micro-structure and method of manufacturing same 有权
    绝缘微结构及其制造方法相同

    公开(公告)号：US06797589B2

    公开(公告)日：2004-09-28

    申请号：US10322990

    申请日：2002-12-18

    Applicant: Scott G. Adams ,  Scott A. Miller

    Inventor： Scott G. Adams ,  Scott A. Miller

    IPC: H01L2176

    CPC classification number: H01L21/76229 ,  B81B3/0086 ,  B81B2203/033 ,  B81C1/00126 ,  B81C2201/0178 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/76208

    Abstract: A method of manufacturing an insulating micro-structure by etching a plurality of trenches in a silicon substrate and filling said trenches with insulating materials. The trenches are etched and then oxidized until completely or almost completely filled with silicon dioxide. Additional insulating material is then deposited as necessary to fill any remaining trenches, thus forming the structure. When the top of the structure is metallized, the insulating structure increases voltage resistance and reduces the capacitive coupling between the metal and the silicon substrate. Part of the silicon substrate underlying the structure is optionally removed further to reduce the capacitive coupling effect. Hybrid silicon-insulator structures can be formed to gain the effect of the benefits of the structure in three-dimensional configurations, and to permit metallization of more than one side of the structure.

    Abstract translation: 通过蚀刻硅衬底中的多个沟槽并用绝缘材料填充所述沟槽来制造绝缘微结构的方法。 蚀刻沟槽，然后氧化直到完全或几乎完全充满二氧化硅。 然后根据需要沉积额外的绝缘材料以填充任何剩余的沟槽，从而形成结构。 当结构的顶部被金属化时，绝缘结构增加了电阻并降低了金属和硅衬底之间的电容耦合。 可选地，进一步去除结构底层的硅衬底的一部分以降低电容耦合效应。 可以形成混合硅 - 绝缘体结构以获得三维结构中结构的益处的效果，并且允许结构多于一侧的金属化。

    Method for producing optically transparent regions in a silicon substrate
    120.
    发明申请
    Method for producing optically transparent regions in a silicon substrate 有权
    在硅衬底中制造光学透明区域的方法

    公开(公告)号：US20040155010A1

    公开(公告)日：2004-08-12

    申请号：US10474968

    申请日：2004-03-31

    Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

    IPC: B29D011/00

    CPC classification number: B81B3/0083 ,  B81B2203/0315 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/0178 ,  C25F3/12 ,  C25F3/14 ,  H01L21/306 ,  H01L21/3081

    Abstract: A simple and cost-effective possibility is proposed for producing optically transparent regions (5, 6) in a silicon substrate (1), by the use of which both optically transparent regions of any thickness and optically transparent regions over a cavity in a silicon substrate are able to be implemented. For this purpose, first at least a specified region (5, 6) of the silicon substrate (1) is etched porous. Thereafter, the specified porous region (5, 6) of the silicon substrate (1) is oxidized.

    Abstract translation: 提出了在硅衬底（1）中制造光学透明区域（5,6）的简单和成本有效的可能性，其中通过在硅衬底的空腔上使用任何厚度和光学透明区域的两个光学透明区域 能够实施。 为此目的，首先对硅衬底（1）的至少一个特定区域（5,6）进行多孔蚀刻。 此后，硅衬底（1）的规定的多孔区域（5,6）被氧化。

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