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公开(公告)号：US20100291488A1
公开(公告)日：2010-11-18
申请号：US12805371
申请日：2010-07-27
Applicant: Soon-Oh Jung , Cheol-Ho Choi , Chang-Hyun Nam , Hong-Won Kim , Seung-Chul Kim
Inventor： Soon-Oh Jung , Cheol-Ho Choi , Chang-Hyun Nam , Hong-Won Kim , Seung-Chul Kim
CPC classification number: H05K3/108 , H05K3/181 , H05K3/4661 , H05K2201/0344 , Y10T29/49124 , Y10T428/31678
Abstract: A method for manufacturing a cone board including: preparing a core insulation layer including one or more resins selected from the group consisting of epoxy resins and bismaleimide triazine resins; and forming a first nickel layer on at least one surface of the core insulation layer by electroless plating
Abstract translation: 一种锥形板的制造方法，包括：制备包含一种或多种选自环氧树脂和双马来酰亚胺三嗪树脂的树脂的芯绝缘层; 以及通过无电镀在所述芯绝缘层的至少一个表面上形成第一镍层
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112.发明授权公开(公告)号：US07827680B2
公开(公告)日：2010-11-09
申请号：US10751428
申请日：2004-01-06
Applicant: Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
Inventor： Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
IPC: H05K3/20
CPC classification number: H05K3/4644 , C23C18/1607 , C23C18/1653 , C23C18/22 , C23C18/30 , C23C18/34 , C23C18/405 , C23C28/00 , C23C28/023 , C23C28/42 , C25D3/38 , C25D5/022 , C25D5/18 , C25D5/34 , C25D7/123 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K3/0038 , H05K3/108 , H05K3/181 , H05K3/241 , H05K3/381 , H05K3/382 , H05K3/384 , H05K3/421 , H05K3/423 , H05K3/427 , H05K3/4602 , H05K3/4652 , H05K3/4661 , H05K2201/0215 , H05K2201/0344 , H05K2201/0347 , H05K2201/09509 , H05K2201/09536 , H05K2201/09563 , H05K2201/0959 , H05K2201/096 , H05K2203/0353 , H05K2203/0723 , H05K2203/1476 , H05K2203/1492 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
Abstract: An electroplating process of electroplating an electrically conductive substrate is described. The process includes electroplating intermittently to a predetermined plating thickness using the substrate surface as a cathode and a plating metal as an anode at a constant voltage between the anode and the cathode by repeating application of a voltage between a cathode and an anode and interruption of the application alternately. It is described that a voltage time/interruption time ratio is 0.1 to 1.0, a voltage time is not longer than 10 seconds, and an interruption time is not less than 1 x 10-12 seconds.
Abstract translation: 描述了对导电基板进行电镀的电镀工艺。 该工艺包括通过在阴极和阳极之间重复施加电压并使阴极和阳极之间的电压中断，在阳极和阴极之间以恒定电压将衬底表面作为阴极和电镀金属作为阳极间歇地电镀到预定的镀层厚度 交替应用。 描述了电压时间/中断时间比为0.1至1.0，电压时间不长于10秒，并且中断时间不小于1×10-12秒。
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公开(公告)号：US07691189B2
公开(公告)日：2010-04-06
申请号：US11736495
申请日：2007-04-17
Applicant: Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
Inventor： Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
CPC classification number: H05K3/4644 , C23C18/1607 , C23C18/1653 , C23C18/22 , C23C18/30 , C23C18/34 , C23C18/405 , C23C28/00 , C23C28/023 , C23C28/42 , C25D3/38 , C25D5/022 , C25D5/18 , C25D5/34 , C25D7/123 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K3/0038 , H05K3/108 , H05K3/181 , H05K3/241 , H05K3/381 , H05K3/382 , H05K3/384 , H05K3/421 , H05K3/423 , H05K3/427 , H05K3/4602 , H05K3/4652 , H05K3/4661 , H05K2201/0215 , H05K2201/0344 , H05K2201/0347 , H05K2201/09509 , H05K2201/09536 , H05K2201/09563 , H05K2201/0959 , H05K2201/096 , H05K2203/0353 , H05K2203/0723 , H05K2203/1476 , H05K2203/1492 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
Abstract: The present invention is directed to a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity, and by which uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.
Abstract translation: 本发明涉及一种制造多层印刷电路板的方法，该印刷电路板能够同时通孔填充和形成导体电路和具有良好结晶度的通孔，并且可以在基板和高密度布线上构造均匀的沉积 并且可以实现高可靠性的导体连接而不退火。
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公开(公告)号：US20090294296A1
公开(公告)日：2009-12-03
申请号：US12357909
申请日：2009-01-22
Applicant: Jungsup YUM , Dongki KO
Inventor： Jungsup YUM , Dongki KO
IPC: C25D5/54
CPC classification number: H05K3/426 , H05K1/0393 , H05K3/181 , H05K3/422 , H05K2201/0344 , H05K2201/09827
Abstract: A method of manufacturing a flexible film is disclosed. The method includes (a) forming at least one hole on an insulating film, (b) after the step (a), forming a first metal layer on a first surface corresponding to an inner circumferential surface of the hole, and at least one of a second surface corresponding to an upper surface of the insulating film and a third surface corresponding to a lower surface of the insulating film, and (c) forming a second metal layer on the first metal layer. A thickness of the first metal layer is smaller than a thickness of the second metal layer.
Abstract translation: 公开了制造柔性膜的方法。 该方法包括：（a）在绝缘膜上形成至少一个孔，（b）在步骤（a）之后，在对应于该孔的内周表面的第一表面上形成第一金属层，以及至少一个 与所述绝缘膜的上表面对应的第二表面和与所述绝缘膜的下表面对应的第三表面，以及（c）在所述第一金属层上形成第二金属层。 第一金属层的厚度小于第二金属层的厚度。
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公开(公告)号：US20090284443A1
公开(公告)日：2009-11-19
申请号：US12357946
申请日：2009-01-22
Applicant: Jungsup Yum , Dongki Ko
Inventor： Jungsup Yum , Dongki Ko
CPC classification number: H05K3/181 , H05K1/0393 , H05K3/422 , H05K3/426 , H05K2201/0338 , H05K2201/0344 , H05K2201/09827 , Y10T428/12375 , Y10T428/12396 , Y10T428/12472 , Y10T428/12493 , Y10T428/12569 , Y10T428/12771 , Y10T428/12847 , Y10T428/12889 , Y10T428/12903 , Y10T428/1291 , Y10T428/12944
Abstract: A flexible film and a display device including the same are disclosed. The flexible film includes an insulating film including at least one hole. The insulating film further includes a first surface corresponding to an inner circumferential surface of the hole, a second surface corresponding to an upper surface of the insulating film, and a third surface corresponding to a lower surface of the insulating film. The flexible film includes a first metal layer and a second metal layer that is positioned on the first surface and at least one of the second and third surfaces. A thickness of the first metal layer is smaller than a thickness of the second metal layer.
Abstract translation: 公开了一种柔性膜和包括该柔性膜的显示装置。 柔性膜包括包括至少一个孔的绝缘膜。 绝缘膜还包括对应于孔的内周面的第一表面，对应于绝缘膜的上表面的第二表面和对应于绝缘膜的下表面的第三表面。 柔性膜包括第一金属层和位于第一表面上的第二金属层和第二表面和第三表面中的至少一个。 第一金属层的厚度小于第二金属层的厚度。
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Patent Agency Ranking
116.发明申请公开(公告)号：US20080003351A1
公开(公告)日：2008-01-03
申请号：US11899256
申请日：2007-09-04
Applicant: Peter Kukanskis , Dennis Fritz , Frank Durso , Steven Castaldi , David Sawoska
Inventor： Peter Kukanskis , Dennis Fritz , Frank Durso , Steven Castaldi , David Sawoska
IPC: H05K3/06
CPC classification number: H01C17/24 , H01C17/242 , H05K1/167 , H05K3/027 , H05K3/064 , H05K3/184 , H05K2201/0344 , H05K2203/0315 , H05K2203/107 , H05K2203/1105 , H05K2203/1453 , H05K2203/171
Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.
Abstract translation: 揭示了一种工艺，其中电阻器可以通过将电阻器电镀到绝缘基板上而与印刷电路板一体制造。 作为用于改善镀覆电阻器的均匀性和一致性的技术，讨论了绝缘衬底通过电镀电阻器的蚀刻和氧化的均匀化。 还公开了修整和烘烤作为用于调节和稳定电镀电阻器的电阻的方法。
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公开(公告)号：US20070266886A1
公开(公告)日：2007-11-22
申请号：US11736495
申请日：2007-04-17
Applicant: Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
Inventor： Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
IPC: C09D5/00
CPC classification number: H05K3/4644 , C23C18/1607 , C23C18/1653 , C23C18/22 , C23C18/30 , C23C18/34 , C23C18/405 , C23C28/00 , C23C28/023 , C23C28/42 , C25D3/38 , C25D5/022 , C25D5/18 , C25D5/34 , C25D7/123 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K3/0038 , H05K3/108 , H05K3/181 , H05K3/241 , H05K3/381 , H05K3/382 , H05K3/384 , H05K3/421 , H05K3/423 , H05K3/427 , H05K3/4602 , H05K3/4652 , H05K3/4661 , H05K2201/0215 , H05K2201/0344 , H05K2201/0347 , H05K2201/09509 , H05K2201/09536 , H05K2201/09563 , H05K2201/0959 , H05K2201/096 , H05K2203/0353 , H05K2203/0723 , H05K2203/1476 , H05K2203/1492 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.
Abstract translation: 本发明的目的是提供一种制造多层印刷电路板的方法，其能够同时通孔填充和形成导体电路，并且可以在基板和高密度布线上构造具有良好结晶度和均匀沉积的通孔 并且可以实现高可靠性的导体连接而不退火。 本发明涉及一种多层印刷电路板的制造方法，其特征在于，在形成有导体电路的基板上设置层间树脂绝缘层，在所述层间树脂绝缘层上形成用于形成通孔的开口，形成无电镀金属 层，在其上设置抗蚀剂，进行电镀，剥离抗蚀剂并蚀刻无电镀金属层以提供导体电路和通孔，其中使用所述无电镀金属层作为阴极间歇地进行电镀 以及在所述阳极和所述阴极之间的恒定电压下的电镀金属作为阳极。
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118.发明申请公开(公告)号：US20070224346A1
公开(公告)日：2007-09-27
申请号：US11386631
申请日：2006-03-22
Applicant: Mark Wojtaszek , James Watkowski , Gary Larson , Peter Kukanskis
Inventor： Mark Wojtaszek , James Watkowski , Gary Larson , Peter Kukanskis
CPC classification number: H05K3/181 , C08J7/12 , C08J7/123 , C08J2379/08 , C23C18/1651 , C23C18/1653 , C23C18/2006 , C23C18/2086 , C23C18/22 , C23C18/30 , C23C18/32 , H05K1/0346 , H05K3/381 , H05K2201/0344 , H05K2203/0793 , H05K2203/095 , H05K2203/097
Abstract: The present invention is directed to an improved method for metallizing polymer substrates, such as polyimides. The present invention comprises the steps of surface treating the polymer substrate with a plasma jet or corona discharge surface treatment, conditioning and etching the polymer substrate with an etching solution comprising a hydroxide and ionic palladium, activating the polymer substrate with ionic palladium, reducing the palladium on the polymer substrate, plating an electroless nickel layer onto the prepared polymer substrate, and plating an electroless copper layer over the electroless nickel layer. The process of the invention provides an improved method for preparing the polymer substrate for subsequent electrolytic plating thereon.
Abstract translation: 本发明涉及用于金属化聚合物基材例如聚酰亚胺的改进方法。 本发明包括以下步骤：用等离子体喷射或电晕放电表面处理对聚合物基材进行表面处理，用包含氢氧化物和离子钯的蚀刻溶液调节和蚀刻聚合物基材，用离子钯活化聚合物底物，还原钯 在聚合物基材上，将无电镍层电镀到制备的聚合物基材上，并在化学镀镍层上镀覆无电解铜层。 本发明的方法提供了一种改进的制备聚合物基质的方法，用于其后的电解电镀。
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公开(公告)号：US20070212871A1
公开(公告)日：2007-09-13
申请号：US11716720
申请日：2007-03-09
Applicant: Satoshi Kimura , Hidemichi Furihata , Toshihiko Kaneda
Inventor： Satoshi Kimura , Hidemichi Furihata , Toshihiko Kaneda
IPC: H01L21/4763
CPC classification number: H01L21/288 , C23C18/1608 , C23C18/1651 , C23C18/1893 , C23C18/2086 , C23C18/30 , C23C18/34 , C23C18/40 , C23C18/54 , H01L21/76885 , H05K3/184 , H05K3/24 , H05K2201/0344 , H05K2203/0565 , H05K2203/073
Abstract: A method of manufacturing an interconnect substrate by electroless plating, including: (a) forming a catalyst layer with a specific pattern on a substrate; (b) immersing the substrate in a first electroless plating solution including a first metal to deposit the first metal on the catalyst layer to form a first metal layer; and (c) immersing the substrate in a second electroless plating solution including a second metal to deposit the second metal on the first metal layer to form a second metal layer, an ionization tendency of the first metal being higher than an ionization tendency of the second metal.
Abstract translation: 一种通过化学镀制造互连基板的方法，包括：（a）在基板上形成具有特定图案的催化剂层; （b）将基板浸入包含第一金属的第一非电镀溶液中以将第一金属沉积在催化剂层上以形成第一金属层; 以及（c）将所述基板浸渍在包含第二金属的第二非电解镀液中以将所述第二金属沉积在所述第一金属层上以形成第二金属层，所述第一金属的电离倾向高于所述第二金属的电离倾向 金属。
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公开(公告)号：US07034231B2
公开(公告)日：2006-04-25
申请号：US10419651
申请日：2003-04-21
Applicant: Peter Kukanskis , Dennis Fritz , Frank Durso , Steven Castaldi , David Sawoska
Inventor： Peter Kukanskis , Dennis Fritz , Frank Durso , Steven Castaldi , David Sawoska
IPC: H05K1/16
CPC classification number: H01C17/24 , H01C17/242 , H05K1/167 , H05K3/027 , H05K3/064 , H05K3/184 , H05K2201/0344 , H05K2203/0315 , H05K2203/107 , H05K2203/1105 , H05K2203/1453 , H05K2203/171
Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.
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