公开(公告)号：US20240032196A1

公开(公告)日：2024-01-25

申请号：US18043356

申请日：2020-09-07

Applicant: GOERTEK TECHNOLOGY CO., LTD.

Inventor： Kenichiro KODAMA

IPC: H05K1/14 ,  H05K1/02

CPC classification number: H05K1/142 ,  H05K1/025 ,  H05K1/028 ,  H05K2201/10098 ,  H05K2201/10196 ,  H05K2201/10045

Abstract: An electronic device includes a first circuit operating on a first signal of a first frequency and a second circuit operating on a second signal of a second frequency. The first signal is different from the second signal, and the first circuit and the second circuit share a first component. The first component functions as an antenna for the second circuit, which reduces space occupied by a dedicated or independent antenna and achieves smaller size and better industrial design for the electronic device.

公开(公告)号：US11653441B2

公开(公告)日：2023-05-16

申请号：US16951695

申请日：2020-11-18

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Julien Didion ,  Thierry Lapergue

IPC: H05K1/02 ,  H04B1/16 ,  H05K1/18

CPC classification number: H05K1/025 ,  H04B1/16 ,  H05K1/181 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10045 ,  H05K2201/10098

Abstract: A device includes a printed circuit board substrate, an antenna connected to the printed circuit board substrate, an amplifier connected to the printed circuit board substrate, and a matching track having a first end electrically connected to an input of the amplifier and a second end electrically connected to an output of the antenna. The matching track has an outgrowth that is symmetrical along a median axis of the outgrowth. The matching track is rectilinear and has a constant width over an initial part extending between the widening area and the first end. A median axis of the initial part and the median axis of the outgrowth form an angle comprised between 60 and 120°.

公开(公告)号：US09685273B2

公开(公告)日：2017-06-20

申请号：US15051648

申请日：2016-02-23

Applicant: ROHM CO., LTD.

Inventor： Hiroki Yamamoto ,  Keishi Watanabe ,  Hiroshi Tamagawa

IPC: H01L27/00 ,  H01G4/30 ,  H01L23/522 ,  H01L27/10 ,  H01L27/24 ,  H01L23/00 ,  H01G4/40 ,  H01L29/66 ,  H01L29/94 ,  H01G2/06 ,  H05K1/11 ,  H05K1/16 ,  H05K1/18 ,  H01L21/66 ,  H01L27/06 ,  H01G4/005 ,  H01G4/228 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/005 ,  H01G4/228 ,  H01G4/232 ,  H01G4/40 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5223 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/101 ,  H01L27/2409 ,  H01L28/40 ,  H01L29/66189 ,  H01L29/94 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/162 ,  H05K1/18 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10045 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

公开(公告)号：US09215807B2

公开(公告)日：2015-12-15

申请号：US13626858

申请日：2012-09-25

Applicant: Shawn X. Arnold ,  Jeffrey M. Thoma

Inventor： Shawn X. Arnold ,  Jeffrey M. Thoma

IPC: H05K1/14 ,  H05K1/02 ,  H05K1/11 ,  H05K3/36

CPC classification number: H05K1/141 ,  H05K1/0231 ,  H05K1/111 ,  H05K3/366 ,  H05K2201/049 ,  H05K2201/10045 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49133

Abstract: The described embodiments relate generally to electronic components and more specifically to a capacitor array that can increase component density on a printed circuit board and reduce a distance to a ground plane. An array of capacitors can be formed by coupling a group of capacitors on their sides interspersed with interposer boards. The resulting configuration can increase component density and reduce an amount of resistance and effective series inductance between a set of power decoupling capacitors and an integrated circuit.

Abstract translation: 所描述的实施例一般涉及电子部件，更具体地涉及可以增加印刷电路板上的部件密度并减小到接地平面的距离的电容器阵列。 一组电容器可以通过将一组电容器连接在插入有插入板的侧面上形成。 所得到的配置可以增加组件密度并减少一组功率去耦电容器和集成电路之间的电阻和有效串联电感量。

公开(公告)号：US08461463B2

公开(公告)日：2013-06-11

申请号：US13080783

申请日：2011-04-06

Applicant: Noboru Kato ,  Jun Sasaki ,  Katsumi Taniguchi

Inventor： Noboru Kato ,  Jun Sasaki ,  Katsumi Taniguchi

IPC: H05K1/16

CPC classification number: H05K1/186 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/19106 ,  H05K1/141 ,  H05K1/165 ,  H05K3/284 ,  H05K2201/09481 ,  H05K2201/10045 ,  H05K2203/1316

Abstract: A composite module is obtained which enables high-density mounting of components without increasing its size. A composite module includes a main substrate which is a multilayer circuit board, a sub-substrate mounted on a lower surface of the main substrate, a sealing layer arranged on the lower surface of the main substrate to cover the sub-substrate, the sealing layer defining a mount surface arranged to be mounted on a mount board, and terminal electrodes disposed on the mount surface. The terminal electrodes include at least one first terminal electrode drawn directly from the main substrate and at least one second terminal electrode drawn directly from the sub-substrate.

Abstract translation: 获得了组合模块，其可以在不增加其尺寸的情况下实现组件的高密度安装。 复合模块包括作为多层电路板的主衬底，安装在主衬底的下表面上的子衬底，设置在主衬底的下表面以覆盖副衬底的密封层，密封层 限定安装在安装板上的安装表面和设置在安装表面上的端子电极。 端子电极包括从主衬底直接绘制的至少一个第一端子电极和直接从该辅助衬底引出的至少一个第二端子电极。

公开(公告)号：US20110182039A1

公开(公告)日：2011-07-28

申请号：US13080783

申请日：2011-04-06

Applicant: Noboru KATO ,  Jun SASAKI ,  Katsumi TANIGUCHI

Inventor： Noboru KATO ,  Jun SASAKI ,  Katsumi TANIGUCHI

IPC: H05K1/14

CPC classification number: H05K1/186 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/19106 ,  H05K1/141 ,  H05K1/165 ,  H05K3/284 ,  H05K2201/09481 ,  H05K2201/10045 ,  H05K2203/1316

Abstract: A composite module is obtained which enables high-density mounting of components without increasing its size. A composite module includes a main substrate which is a multilayer circuit board, a sub-substrate mounted on a lower surface of the main substrate, a sealing layer arranged on the lower surface of the main substrate to cover the sub-substrate, the sealing layer defining a mount surface arranged to be mounted on a mount board, and terminal electrodes disposed on the mount surface. The terminal electrodes include at least one first terminal electrode drawn directly from the main substrate and at least one second terminal electrode drawn directly from the sub-substrate.

Abstract translation: 获得了组合模块，其可以在不增加其尺寸的情况下实现组件的高密度安装。 复合模块包括作为多层电路板的主衬底，安装在主衬底的下表面上的子衬底，设置在主衬底的下表面以覆盖副衬底的密封层，密封层 限定安装在安装板上的安装表面和设置在安装表面上的端子电极。 端子电极包括从主衬底直接绘制的至少一个第一端子电极和直接从该辅助衬底引出的至少一个第二端子电极。

公开(公告)号：US07515434B2

公开(公告)日：2009-04-07

申请号：US11014962

申请日：2004-12-20

Applicant: Aneta Wyrzykowska ,  Herman Kwong ,  Kah Ming Soh

Inventor： Aneta Wyrzykowska ,  Herman Kwong ,  Kah Ming Soh

IPC: H05K1/18

CPC classification number: H05K1/0246 ,  H01L2224/16225 ,  H05K1/023 ,  H05K1/141 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/184 ,  H05K3/4046 ,  H05K3/4053 ,  H05K2201/0187 ,  H05K2201/10045 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A technique for enhancing circuit density and performance is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for enhancing circuit density and performance of a microelectronic module. The method may comprise forming a discrete package, wherein the discrete package comprises one or more passive devices that are desirable for the performance of the microelectronic module. The method may also comprise coupling the discrete package to the microelectronic module.

Abstract translation: 公开了一种用于增强电路密度和性能的技术。 在一个特定的示例性实施例中，该技术可以被实现为用于增强微电子模块的电路密度和性能的方法。 该方法可以包括形成分立封装，其中分立封装包括对微电子模块执行所期望的一个或多个无源器件。 该方法还可以包括将分立封装耦合到微电子模块。

公开(公告)号：US20080136580A1

公开(公告)日：2008-06-12

申请号：US11947422

申请日：2007-11-29

Applicant: Hyo-Jae BANG ,  Dong-Chun LEE ,  Seong-Chan HAN ,  Jung-Hyeon KIM ,  Hyun-Seok CHOI

Inventor： Hyo-Jae BANG ,  Dong-Chun LEE ,  Seong-Chan HAN ,  Jung-Hyeon KIM ,  Hyun-Seok CHOI

IPC: H01C1/01

CPC classification number: H01C1/144 ,  H01C1/01 ,  H01C7/18 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/09172 ,  H05K2201/10045 ,  Y02P70/613

Abstract: Provided are a chip network resistor contacting a printed circuit board (PCB) through solder balls and a semiconductor module having the chip network resistor. The chip network resistor includes: a body formed of an insulating material; a resistor formed on the body; external electrodes connected to the resistor and disposed on a lower surface of the body so as to have solder ball pad shapes; and conductive balls adhered on the external electrodes.

Abstract translation: 提供了通过焊球与印刷电路板（PCB）接触的芯片网络电阻器和具有芯片网络电阻器的半导体模块。 芯片网络电阻器包括：由绝缘材料形成的主体; 形成在体上的电阻; 外部电极连接到电阻器并且设置在主体的下表面上以具有焊球形状; 并且导电球附着在外部电极上。

公开(公告)号：US20070076392A1

公开(公告)日：2007-04-05

申请号：US11513034

申请日：2006-08-31

Applicant: Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

Inventor： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01G2/06 ,  H01G4/40 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0233 ,  H05K1/0234 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wiring board comprising: a board core (11) having a core main surface (12) and a core reverse surface (13); a capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) having a capacitor main surface (102) and a capacitor reverse surface (103) and having a structure in which first inner electrode layers (141) and second inner electrode layers (142) are alternately laminated and arranged via a dielectric layer (105), the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) being accommodated in the board core (11) in a state in which the core main surface (12) and the capacitor main surface (102) are oriented on a same side; and a wiring laminated portion (31) having a structure in which interlayer insulating layers (33, 35) and conductor layers (42) are alternately laminated on the core main surface (12) and the capacitor main surface (102), wherein an inductor (251, 252, 253) or a resistor (301, 302, 311, 312, 321, 322) is formed on or in the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″).

Abstract translation: 一种布线板，包括：具有芯主表面（12）和芯反向表面（13）的板芯（11）; 一个电容器（101,101A，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101'，1101“，1101”'，1101“ 具有电容器主表面（102）和电容器反面（103）的第一内电极层（141）和第二内电极层（142）交替层叠的结构的电容器（1101“'），1101” 电容器（101,101A，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101），1101“，经由电介质层（105） 1101“，1101”“，1101”“”）以芯主表面（12）和电容器主表面（102）取向为的状态容纳在板芯（11）中 同一边 以及具有层间绝缘层（33,35）和导体层（42）交替层叠在芯主表面（12）和电容器主表面（102）上的结构的布线层叠部分（31），其中电感器 （101,21A，101B，101C，101D，101E，101F）上形成有电阻（251,252,253）或电阻器（301,302,311,312,321,322） ，101G，101H，101J，1101,1101'，1101“，1101”'，1101“'，1101”''）。

公开(公告)号：US20070013442A1

公开(公告)日：2007-01-18

申请号：US11452405

申请日：2006-06-14

Applicant: Dirk Wiegner ,  Thomas Merk

Inventor： Dirk Wiegner ,  Thomas Merk

IPC: H03F1/00

CPC classification number: H03F3/195 ,  H03F2200/144 ,  H03F2200/147 ,  H03F2200/451 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/10045 ,  H05K2201/10166 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611

Abstract: An amplifier, in particular for RF-applications, comprises a circuit board (2), at least one amplifier stage with at least one transistor package (8) arranged on the circuit board (2), and a feedback path (12) around the at least one transistor package (8), said feedback path (12) comprising a feedback element (15) with at least one capactive (C) element for blocking the flow of direct current through the feedback path (12) and preferably further comprising at least one inductive (L) and/or resistive element (R). In order to reduce negative effects on the performance of the amplifier due to long printed feedback lines, the feedback path (12) in an amplifier according to the invention is formed of a feedback bridge (9) comprising two feedback lines (13, 14) extending out of the plane of the circuit board (2) from two contact flags (10, 11) of the transistor package (8), and the feedback element (15) bridging over the transistor package (8) between the two feedback lines (13, 14).

Abstract translation: 特别是用于RF应用的放大器包括电路板（2），至少一个具有布置在电路板（2）上的至少一个晶体管封装（8）的放大器级，以及围绕 至少一个晶体管封装（8），所述反馈路径（12）包括具有至少一个负载（C）元件的反馈元件（15），用于阻断通过所述反馈路径（12）的直流电流，并且优选地还包括 至少一个电感（L）和/或电阻元件（R）。 为了减少由于长的印刷反馈线引起的放大器的性能的负面影响，根据本发明的放大器中的反馈路径（12）由包括两个反馈线（13,14）的反馈桥（9）形成， 从晶体管封装（8）的两个接触标记（10,11）延伸出电路板（2）的平面，并且反馈元件（15）跨接在两个反馈线之间的晶体管封装（8）上 13,14）。