公开(公告)号：DE10315050B4

公开(公告)日：2009-04-23

申请号：DE10315050

申请日：2003-04-02

Applicant: IBM ,  QIMONDA AG

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD ,  HANSON DAVID

IPC: H03K19/0185 ,  H03L5/00

Abstract: A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

公开(公告)号：DE60035630T2

公开(公告)日：2008-02-07

申请号：DE60035630

申请日：2000-01-22

Applicant: IBM ,  QIMONDA NORTH AMERICA CORP

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

公开(公告)号：DE69834540T2

公开(公告)日：2007-05-03

申请号：DE69834540

申请日：1998-12-18

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C7/00 ,  G11C11/401 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14 ,  G11C11/408 ,  G11C11/409 ,  G11C16/06

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F , includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

公开(公告)号：DE10314615B4

公开(公告)日：2006-12-21

申请号：DE10314615

申请日：2003-04-01

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/22 ,  H03F3/04 ,  H03K19/0175 ,  H03K19/094

Abstract: A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.

公开(公告)号：DE69833093T2

公开(公告)日：2006-08-31

申请号：DE69833093

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  WONG HING ,  KRSNKI BOZIDAR

IPC: G01R31/28 ,  G11C29/56 ,  G11C7/12 ,  G11C11/401 ,  G11C29/04 ,  G11C29/14 ,  G11C29/50

Abstract: The method involves generating a dummy timing cycle for disabling bitline equalizer by supplying a negative test pulse. The bitline equaliser is disabled to set up a floating bitline test mode. A row address strobe signal is enabled and read operation is started in a normal mode. Defective bitlines are detected during dummy timing cycles.

公开(公告)号：DE60010338T2

公开(公告)日：2005-06-16

申请号：DE60010338

申请日：2000-12-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HANSON R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  H03K17/22 ,  H03K19/0175

Abstract: A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.

公开(公告)号：DE69911364T2

公开(公告)日：2004-07-22

申请号：DE69911364

申请日：1999-12-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G06F11/20

Abstract: The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.

公开(公告)号：GB2352855B

公开(公告)日：2004-04-14

申请号：GB0009818

申请日：2000-04-25

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  G06F11/20

Abstract: A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

公开(公告)号：GB2355327B

公开(公告)日：2004-02-18

申请号：GB0017095

申请日：2000-07-13

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  STORASKA DANIEL ,  NARAYAN CHANDRASEKHAR ,  TONTI WILLIAM ,  BERTIN CLAUDE ,  VAN HEEL NICK

IPC: G11C14/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/04 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/112

Abstract: A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.

公开(公告)号：DE60006720D1

公开(公告)日：2003-12-24

申请号：DE60006720

申请日：2000-12-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/10 ,  G11C7/00

Abstract: A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.