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187 records (took 0.022 seconds)

    121.
    发明专利
    未知

    公开(公告)号：DE69324020T2

    公开(公告)日：1999-07-15

    申请号：DE69324020

    申请日：1993-12-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

    IPC: H01L21/82 ,  G11C29/00 ,  H01L27/10 ,  G06F11/20

    Abstract: A redundancy circuitry for a semiconductor memory device comprising a matrix of memory elements, comprises a plurality of programmable non-volatile memory registers (1), which are programmable to store addresses of defective memory elements which must be replaced by redundancy memory elements; the redundancy circuitry comprises combinatorial circuit means (3) supplied by address signals (ADD) and supplying the non-volatile registers (1) with an inhibition signal (DIS) for inhibiting the selection of redundancy memory elements when a memory element of the matrix is addressed whose address coincides with the address stored in a non-programmed memory register (1).

    123.
    发明专利
    未知

    公开(公告)号：DE69324020D1

    公开(公告)日：1999-04-22

    申请号：DE69324020

    申请日：1993-12-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

    IPC: H01L21/82 ,  G11C29/00 ,  H01L27/10 ,  G06F11/20

    Abstract: A redundancy circuitry for a semiconductor memory device comprising a matrix of memory elements, comprises a plurality of programmable non-volatile memory registers (1), which are programmable to store addresses of defective memory elements which must be replaced by redundancy memory elements; the redundancy circuitry comprises combinatorial circuit means (3) supplied by address signals (ADD) and supplying the non-volatile registers (1) with an inhibition signal (DIS) for inhibiting the selection of redundancy memory elements when a memory element of the matrix is addressed whose address coincides with the address stored in a non-programmed memory register (1).

    124.
    发明专利
    未知

    公开(公告)号：DE69222249D1

    公开(公告)日：1997-10-23

    申请号：DE69222249

    申请日：1992-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C7/00 ,  G11C5/06

    Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by implifying the sensing process.

    125.
    发明专利
    未知

    公开(公告)号：IT1253678B

    公开(公告)日：1995-08-22

    申请号：ITVA910022

    申请日：1991-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C

    Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by implifying the sensing process.

    Dynamic reference system for readout amplifier
    127.
    发明专利
    Dynamic reference system for readout amplifier 未知

    公开(公告)号：IT1253598B

    公开(公告)日：1995-08-22

    申请号：ITVA910042

    申请日：1991-11-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C20060101 ,  G11C

    Abstract: A "dynamic" reference system for sense-amplifier is realised by utilising the dual signals generated at the respective output nodes of the two cascode circuits normally used to control the switches connecting the loads to the respective lines or to the sensing lines, in order to control two imbalance transistors of essentially different dimension from each other, functionally connected between the switches and a source of polarisation current, in order to superimpose an offset current on the current forced across the loads of the two lines of the input network so as to enable a discrimination even in the event of identical selected locations. The reference system is simple to construct and offers numerous advantages with respect to the "static" reference systems of the prior art.

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