公开(公告)号：US20170098707A1

公开(公告)日：2017-04-06

申请号：US14932993

申请日：2015-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yi-Kuan Wu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/31 ,  H01L27/088 ,  H01L21/285 ,  H01L29/26 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L27/088 ,  H01L21/02521 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/31 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66969

Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.

公开(公告)号：US09548239B2

公开(公告)日：2017-01-17

申请号：US14612235

申请日：2015-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Feng-Yi Chang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Yi-Kuan Wu ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/76 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76816 ,  H01L21/76879

Abstract: A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on the ILD layer and the gate structure, an opening is formed in the dielectric layer and the ILD layer, and an organic dielectric layer (ODL) is formed on the dielectric layer and in the opening. After removing part of the ODL, part of the dielectric layer to extend the opening, and then the remaining ODL, a contact plug is formed in the opening.

Abstract translation: 首先在衬底上形成栅极结构，并且在栅极结构周围形成层间电介质（ILD）层，在ILD层和栅极结构上形成介电层，在介电层和ILD层中形成开口 并且在介质层和开口中形成有机电介质层（ODL）。 在去除部分ODL后，部分电介质层延伸开口，然后剩余的ODL，在开口处形成接触塞。

公开(公告)号：US20170012033A1

公开(公告)日：2017-01-12

申请号：US14817186

申请日：2015-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L27/02 ,  H01L23/535 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a first edge and a second edge extending along a first direction; and a plurality of patterns on the substrate extending along the first direction, in which the patterns includes a plurality of first patterns and a plurality of second patterns, and one of the first patterns closest to the first edge and one of the second patterns closest to the second edge are different.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：具有限定在其上的单元区域的衬底，其中单元区域包括沿着第一方向延伸的第一边缘和第二边缘; 以及沿着所述第一方向延伸的所述基板上的多个图案，其中所述图案包括多个第一图案和多个第二图案，以及最靠近所述第一边缘的所述第一图案中的一个以及最接近 第二个边缘是不同的。

公开(公告)号：US09496396B1

公开(公告)日：2016-11-15

申请号：US14961902

申请日：2015-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Sheng-Hsu Liu ,  Chieh-Lung Wu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/24 ,  H01L29/08

CPC classification number: H01L29/24 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a gate structure on the substrate; (c) performing a first deposition process to form a first epitaxial layer adjacent to the gate structure and performing a first etching process to remove part of the first epitaxial layer at the same time; and (d) performing a second etching process to remove part of the first epitaxial layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：（a）提供衬底; （b）在所述基板上形成栅极结构; （c）执行第一沉积工艺以形成与所述栅极结构相邻的第一外延层，并且执行第一蚀刻工艺以同时去除所述第一外延层的一部分; 和（d）执行第二蚀刻工艺以去除第一外延层的一部分。

公开(公告)号：US09412745B1

公开(公告)日：2016-08-09

申请号：US14620212

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L27/32 ,  H01L27/11 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L27/3223 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.

Abstract translation: 提供一种半导体结构，包括基板，多个第一半导体器件，多个第二半导体器件和多个虚拟插槽触点。 衬底具有器件区域，其中器件区域包括第一功能区域和第二功能区域，并且虚设区域设置在其间。 第一半导体器件和多个第一时隙触点设置在第一功能区域中。 第二半导体器件和多个第二槽触点设置在第二功能区域中。 虚拟插槽触点设置在虚拟区域中。

公开(公告)号：US09401417B2

公开(公告)日：2016-07-26

申请号：US14726595

申请日：2015-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Chien-Chung Huang ,  Kok Seen Lew

IPC: H01L21/44 ,  H01L29/66 ,  H01L29/40 ,  H01L29/45 ,  H01L21/265 ,  H01L21/285 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L29/423 ,  H01L23/485

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming an epitaxial layer within a source/drain region of a semiconductor substrate, forming a fluorine-containing layer on the surface of the epitaxial layer, forming a metal gate structure within the gate region after the step of forming the fluorine-containing layer, forming an interlayer dielectric to cover the semiconductor substrate, the epitaxial layer and the metal gate structure, forming a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer, forming a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole so that the fluorine-containing layer is disposed on the periphery of the metal silicide layer.

Abstract translation: 一种制造半导体器件的方法包括：在半导体衬底的源极/漏极区域内形成外延层，在外延层的表面上形成含氟层，在栅极区域之后形成金属栅极结构，步骤 形成含氟层，形成覆盖半导体衬底，外延层和金属栅极结构的层间电介质，形成穿透层间电介质的接触孔，以露出外延层的一部分，在其上形成金属硅化物层 在接触孔的底部的外延层中，使得含氟层设置在金属硅化物层的周围。

公开(公告)号：US20160204103A1

公开(公告)日：2016-07-14

申请号：US14611843

申请日：2015-02-02

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L27/08

CPC classification number: H01L27/0802 ,  H01L27/0629 ,  H01L27/0647 ,  H01L28/20

Abstract: A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different layers, a plurality of stripe segments of the thin-film resistor structure is electrically connected to ensure the thin-film resistor structure with the predetermined resistance and less averting areas in the layout design.

Abstract translation: 提供具有至少一个薄膜电阻器结构的半导体器件结构。 通过位于不同层上的金属插头或金属布线，薄膜电阻器结构的多个条形段电连接，以确保具有预定电阻的薄膜电阻器结构和布局设计中较少的避免区域 。

公开(公告)号：US20160104645A1

公开(公告)日：2016-04-14

申请号：US14536696

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chien-Ting Lin ,  Shih-Fang Tzou ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/823437 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成多个栅极结构; 在栅极结构上形成第一阻挡层; 在所述第一停止层上形成第二停止层; 在所述第二停止层上形成第一电介质层; 在所述第一电介质层中形成多个第一开口以露出所述第二阻挡层; 在所述第一介电层和所述第二停止层中形成多个第二开口以暴露所述第一停止层; 以及去除所述第二停止层的一部分和所述第一停止层的一部分以暴露所述栅极结构。

公开(公告)号：US20160020323A1

公开(公告)日：2016-01-21

申请号：US14463676

申请日：2014-08-20

Applicant: United Microelectronics Corp.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Wen-Jiun Shen ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure.

Abstract translation: 半导体器件包括鳍结构，绝缘结构，突出结构，外延结构和栅极结构。 翅片结构和绝缘结构设置在基板上。 突出结构与基板直接接触，并从绝缘结构部分突出，突出结构为翅片结构。 外延结构设置在翅片结构的顶表面上并完全覆盖翅片结构的顶表面。 此外，外延结构具有弯曲的顶表面。 栅极结构覆盖鳍结构和外延结构。

公开(公告)号：US20160020110A1

公开(公告)日：2016-01-21

申请号：US14462114

申请日：2014-08-18

Applicant: United Microelectronics Corp.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L21/308 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/3086 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上设置至少一个层叠结构。 第一间隔物层，第二间隔物层和第三间隔物层依次形成在基板上并覆盖层叠结构。 第一，第二和第三间隔物材料层被蚀刻以在堆叠结构的侧壁上形成三层间隔结构。 三层间隔结构包括从层叠结构的一侧形成第一间隔物，第二间隔物和第三间隔物，第二间隔物的介电常数小于第一间隔物的介电常数和 第三间隔物的介电常数。