公开(公告)号：EP4369385A1

公开(公告)日：2024-05-15

申请号：EP23197843.8

申请日：2023-09-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： JAIN, Vibhor ,  KENNEY, Crystal R. ,  PEKARIK, John J.

IPC: H01L21/761 ,  H01L21/74 ,  H01L21/762 ,  H01L27/02 ,  H01L21/82 ,  H01L29/10 ,  H01L29/73 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/761 ,  H01L21/74 ,  H01L21/7624 ,  H01L27/0248 ,  H01L29/1083 ,  H01L29/73 ,  H01L29/78606 ,  H01L27/0623 ,  H01L27/1207

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a substrate with trap rich and low resistivity regions and methods of manufacture. The structure includes: a high resistivity semiconductor substrate; an active device over the high resistivity semiconductor substrate; and a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device.

公开(公告)号：EP4358086A1

公开(公告)日：2024-04-24

申请号：EP23192048.9

申请日：2023-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chinthu, Siva Kumar ,  Pasupula, Suresh ,  Dwivedi, Devesh ,  Chiang, Chunsung

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/004220130101 ,  G11C2013/004520130101 ,  G11C2013/005420130101 ,  G11C7/14 ,  G11C7/065 ,  G11C7/08 ,  G11C2207/06320130101 ,  G11C11/1673

Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

公开(公告)号：EP4355051A1

公开(公告)日：2024-04-17

申请号：EP23190756.9

申请日：2023-08-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Seidel, Robert Viktor ,  Jang, Suk Hee ,  Voronova, Anastasia ,  You, Young Seon

IPC: H10B63/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10N70/8833 ,  H10N70/883 ,  H10N70/24 ,  H10N70/011 ,  H10B63/80 ,  H10N70/801 ,  H10N70/821 ,  H10N70/826 ,  H10N70/253

Abstract: The disclosure provides a structure and method for a memory element to confine a metal (e.g., a remaining portion of a metallic residue) with a spacer. A structure (100) according to the disclosure includes a memory element (102) over a first portion of an insulator layer (104). A portion of the memory element includes a sidewall over the insulator layer. A spacer (126) is adjacent the sidewall of the memory element and on the first portion of the insulator layer. A metal-dielectric layer (124) is within an interface between the spacer and the sidewall or an interface between the spacer and the first portion of the insulator layer. The insulator layer includes a second portion adjacent the first portion, and the second portion does not include the memory element, the spacer, and the metal-dielectric layer thereon.

公开(公告)号：EP4354438A1

公开(公告)日：2024-04-17

申请号：EP23187147.6

申请日：2023-07-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gopinath, Venkatesh P. ,  Parvarandeh, Pirooz

IPC: G11C11/54 ,  G06N3/065 ,  G06F7/544 ,  G11C7/10 ,  G11C7/12 ,  G11C13/00 ,  G11C27/02 ,  G11C11/56

CPC classification number: G11C11/54 ,  G11C13/0004 ,  G11C13/004 ,  G11C7/1006 ,  G11C2213/7720130101 ,  G11C13/0028 ,  G06N3/065 ,  G06F7/5443 ,  G11C13/0026 ,  G11C27/026 ,  G11C13/003 ,  G11C7/1039 ,  G11C7/1084 ,  G11C7/12 ,  G11C11/56 ,  G06F2207/481420130101

Abstract: A structure for in-memory pipeline processing includes a memory bank array. Each bank includes single resistor or dual resistor memory elements connected between input nodes, respectively, and bitline(s) (e.g., a single bitline for a single resistor memory element and first and second bitlines for a dual resistor memory element). A feedback buffer is connected to each bitline and a corresponding output node in each bank and a column interconnect line connects corresponding output nodes of all banks in the same column. The initial bank in each row includes amplifiers connected between the input nodes and memory elements and track-and-hold devices (THs) connected to the input nodes to facilitate pipeline processing. Outputs of the amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks.

公开(公告)号：EP4343394A1

公开(公告)日：2024-03-27

申请号：EP23189909.7

申请日：2023-08-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： BIAN, Yusheng ,  LEE, Won Suk

IPC: G02B6/12 ,  G02B6/122

Abstract: Structures for an optical coupler and methods of forming a structure for an optical coupler. The structure comprises a stacked waveguide core including a first waveguide core and a second waveguide core. The first waveguide core includes a first tapered section, and the second waveguide core includes a second tapered section positioned to overlap with the first tapered section. The structure further comprises a third waveguide core including a third tapered section positioned adjacent to the first tapered section of the first waveguide core and the second tapered section of the second waveguide core.

公开(公告)号：EP4333059A1

公开(公告)日：2024-03-06

申请号：EP23182965.6

申请日：2023-07-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： MAHAJAN, Prantik ,  AJAY, . ,  MITRA, Souvick ,  GAUTHIER, Robert J.

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/87

Abstract: Device structures including a silicon-controlled rectifier and methods of forming a device structure including a silicon-controlled rectifier. The device structure comprises a first well and a second well in a semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite from the first conductivity type. The second well adjoins the first well along an interface. A third doped region includes a first portion in the first well and a second portion in the second well, and a gate structure that overlaps with a portion of the second well.

公开(公告)号：EP4333042A2

公开(公告)日：2024-03-06

申请号：EP23186269.9

申请日：2023-07-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： SHARMA, Santosh ,  BENTLEY, Steven

IPC: H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L29/10 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: at least one depletion mode gate (21) on a conductive material over a semiconductor material (14); and at least one enhancement mode gate (19) electrically connected to the at least one depletion mode gate and over the semiconductor material.

公开(公告)号：EP4328961A1

公开(公告)日：2024-02-28

申请号：EP23184338.4

申请日：2023-07-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： ZHAO, Zhixing ,  CHEN, Yiching

IPC: H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/762 ,  G01K7/01

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture and operation. The structure includes: a semiconductor on insulator substrate; an insulator layer under the semiconductor on insulator substrate; a handle substrate under insulator layer; a first well of a first dopant type in the handle substrate; a second well of a second dopant type in the handle substrate, adjacent to the first well; and a back-gate diode at a juncture of the first well and the second well.

公开(公告)号：EP4307024A1

公开(公告)日：2024-01-17

申请号：EP23178578.3

申请日：2023-06-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： WU, Zhuojie ,  BIAN, Yusheng

IPC: G02B6/42

Abstract: Disclosed is a photonic integrated circuit (PIC) structure including a scattering light-based monitor with photodetectors (e.g., PIN and/or avalanche photodiodes) placed adjacent to one or both sides of an end portion (i.e., a coupler) of a waveguide core at an optical interface with another optical device. The photodetectors are placed in such a way as to enable sensing of scattering light emitted from the end portion as light signals are received (e.g., either from the optical device for propagation to the main body of the waveguide core or from the main body for transmission to the optical device). Also disclosed are a monitoring system and method including the PIC chip structure with the above-described scattering light-based monitor. The system and method assess the optical interface using electric signals generated by the photodetectors.

公开(公告)号：EP4300541A1

公开(公告)日：2024-01-03

申请号：EP22202064.6

申请日：2022-10-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： LEVY, Mark D. ,  LIU, Qizhi ,  HWANG, Jeonghyun

IPC: H01L21/02 ,  H01L21/265 ,  H01L23/373 ,  H01L29/10

Abstract: A structure comprising a semiconductor substrate; a buried porous semiconductor material; a semiconductor compound material and at least one device on the semiconductor compound material.