公开(公告)号：US20150318349A1

公开(公告)日：2015-11-05

申请号：US14439514

申请日：2012-11-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L29/06 ,  H01L21/306 ,  H01L29/40 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/28 ,  H01L21/30604 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for manufacturing a fin structure. The method includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; selectively etching the first semiconductor layer of the initial fin so that the first semiconductor layer has a lateral recess; forming an isolation layer having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.

Abstract translation: 一种翅片结构的制造方法。 该方法包括：在衬底上依次形成第一半导体层和第二半导体层; 图案化第二和第一半导体层以形成初始鳍; 选择性地蚀刻初始翅片的第一半导体层，使得第一半导体层具有侧向凹槽; 形成具有填充所述横向凹部的部分的隔离层，其中所述隔离层除了填充所述横向凹部的部分之外具有比所述第一半导体层的顶表面低的第一表面，但高于所述第一半导体层的底表面的顶表面 半导体层，从而限定隔离层上方的翅片; 以及在所述隔离层上形成与所述翅片相交的栅极堆叠。

公开(公告)号：US20150295070A1

公开(公告)日：2015-10-15

申请号：US14441114

申请日：2012-11-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET and a method for manufacturing the same. The method of manufacturing a FinFET includes: forming a punch-through stopper layer on a semiconductor substrate; forming a first semiconductor layer on the punch-through stopper layer; forming source and drain regions in the first semiconductor layer; forming a semiconductor fin from the first semiconductor layer, wherein the source and drain regions are in contact with the semiconductor fin at opposite ends of the semiconductor fin, respectively; and forming a gate stack intersecting the semiconductor fin and including a gate conductor and a gate dielectric interposed between the gate conductor and the semiconductor fin.

Abstract translation: FinFET及其制造方法。 制造FinFET的方法包括：在半导体衬底上形成穿通阻止层; 在穿通阻挡层上形成第一半导体层; 在所述第一半导体层中形成源区和漏区; 从所述第一半导体层形成半导体鳍，其中所述源极和漏极区分别与所述半导体鳍的相对端处的所述半导体鳍接触; 以及形成与所述半导体鳍片相交的栅极堆叠，并且包括插入在所述栅极导体和所述半导体鳍片之间的栅极导体和栅极电介质。

公开(公告)号：US20150287808A1

公开(公告)日：2015-10-08

申请号：US14435616

申请日：2012-10-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/30625 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78621

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate (200) comprising, from bottom to top, a base layer (201), a buried insulator layer (202), and a surface active layer (203); forming a gate stack on the substrate; removing the surface active layer (203) on both sides of the gate stack and removing a part of the buried insulator layer (202) to form an opening (240); filling the opening (240) with semiconductor materials so as to form source/drain regions (250). Correspondingly, a semiconductor structure is also disclosed. In the present disclosure, by extending the source/drain region to the buried insulator layer of the substrate, the source/drain series resistance is reduced while not increasing parasitic capacitance between the gate and the source/drain regions.

Abstract translation: 公开了半导体结构的制造方法。 该方法包括：提供从底部到顶部包括基底层（201），掩埋绝缘体层（202）和表面活性层（203）的SOI衬底（200）。 在基板上形成栅叠层; 去除所述栅极堆叠的两侧上的表面有源层（203）并且去除所述掩埋绝缘体层（202）的一部分以形成开口（240）; 用半导体材料填充开口（240）以形成源/漏区（250）。 相应地，还公开了一种半导体结构。 在本公开中，通过将源极/漏极区域延伸到衬底的掩埋绝缘体层，源极/漏极串联电阻降低，同时不增加栅极和源极/漏极区域之间的寄生电容。

公开(公告)号：US20150270399A1

公开(公告)日：2015-09-24

申请号：US14439165

申请日：2013-07-31

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/06 ,  H01L21/324 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78603

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate, which comprises, from top to bottom, an SOI layer (100), a BOX layer (110) and a base layer (130); forming a dummy gate stack on the SOI substrate and an implantation barrier layer on both sides of the dummy gate stack; removing the dummy gate stack to form a gate recess (220); and performing, via the gate recess (220), implantation of stress inducing ions to the semiconductor structure and annealing to form, right below the gate recess (220), a stress inducing region (150) under the BOX layer (110) of the SOI substrate. Accordingly, the present invention further provides a semiconductor structure manufactured according to the above method.

Abstract translation: 公开了半导体结构的制造方法。 该方法包括：提供SOI衬底，其从顶部到底部包括SOI层（100），BOX层（110）和基底层（130）; 在SOI衬底上形成虚拟栅极堆叠，在虚设栅极叠层的两侧形成注入阻挡层; 去除所述虚拟栅极堆叠以形成栅极凹部（220）; 以及通过所述栅极凹槽（220），将引入离子的应力注入所述半导体结构并在所述栅极凹部（220）的正下方）退火以形成在所述栅极凹部（220）的所述BOX层（110）下方的应力诱导区域（150） SOI衬底。 因此，本发明还提供根据上述方法制造的半导体结构。

公开(公告)号：US20150262883A1

公开(公告)日：2015-09-17

申请号：US14722597

申请日：2015-05-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Jun Luo ,  Chunlong Li ,  Jian Deng ,  Chao Zhao

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/321 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31105 ,  H01L21/32115 ,  H01L21/32132 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7848

Abstract: A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat.

Abstract translation: 公开了平面化处理。 该方法包括在具有相对高的溅射负载条件的材料层的区域中形成沟槽。 该方法还包括溅射材料层以使材料层平坦。

公开(公告)号：US20150255577A1

公开(公告)日：2015-09-10

申请号：US14430690

申请日：2012-10-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Haizhou Yin ,  Huilong Zhu

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L21/266 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7848

Abstract: A method for manufacturing a MOSFET, including: performing ion implantation, via a shallow trench surrounding an active region in a semiconductor substrate, into a first sidewall of the active region and into a second sidewall of the active region opposite to the first sidewall to form a first heavily doped region in the first sidewall and a second heavily doped region in the second sidewall; filling the shallow trench with an insulating material, to form a shallow trench isolation; forming a gate stack and an insulating layer on the substrate, wherein the insulating layer surrounds and caps the gate stack; forming openings in the substrate using the shallow trench isolation, the first and second heavily doped regions, and the insulating layer as a hard mask; and epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a seed layer.

Abstract translation: 一种用于制造MOSFET的方法，包括：通过围绕半导体衬底中的有源区的浅沟槽进行离子注入到有源区的第一侧壁中并进入与第一侧壁相对的有源区的第二侧壁，以形成 第一侧壁中的第一重掺杂区域和第二侧壁中的第二重掺杂区域; 用绝缘材料填充浅沟槽，形成浅沟槽隔离; 在所述基板上形成栅叠层和绝缘层，其中所述绝缘层围绕并覆盖所述栅叠层; 使用浅沟槽隔离，第一和第二重掺杂区域和作为硬掩模的绝缘层在衬底中形成开口; 并且外延生长具有每个开口的底表面和侧壁的半导体层作为种子层。

公开(公告)号：US20150255557A1

公开(公告)日：2015-09-10

申请号：US14722684

申请日：2015-05-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L29/423 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/45 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42372 ,  H01L21/2652 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin on a semiconductor substrate. The method further includes forming an interfacial oxide layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a high K gate dielectric layer on the interfacial oxide layer. The method further includes forming a first metal gate layer on the high K gate dielectric layer. The method further includes implanting dopant to the first metal gate layer through conformal doping. The method further includes performing annealing so that the dopants are diffused and accumulated at an upper interface between the high K gate dielectric layer and the first metal gate layer, as well as at a lower interface between the high K gate dielectric layer and the interfacial oxide layer, generating electrical dipoles at the lower interface through interfacial reaction.

Abstract translation: 公开了一种半导体器件及其制造方法。 该方法包括在半导体衬底上形成半导体鳍片。 该方法还包括在半导体鳍片的顶表面和侧壁上形成界面氧化物层。 该方法还包括在界面氧化物层上形成高K栅极电介质层。 该方法还包括在高K栅介质层上形成第一金属栅极层。 该方法还包括通过共形掺杂将掺杂剂注入第一金属栅极层。 该方法还包括执行退火，使得掺杂剂在高K栅极介电层和第一金属栅极层之间以及在高K栅极介电层和界面氧化物之间的较低界面处扩散和积聚 层，通过界面反应在下界面产生电偶极子。

公开(公告)号：US09111863B2

公开(公告)日：2015-08-18

申请号：US14119869

申请日：2012-12-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/513 ,  H01L29/66545

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.

Abstract translation: 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层，并修剪硬掩模层，使得修整的硬掩模层具有小于或等于22nm的宽度; 并根据修整的硬掩模层蚀刻顶层非晶硅，ONO结构的硬掩模和底层非晶硅，以及去除硬掩模层和顶层非晶硅。

公开(公告)号：US20150228480A1

公开(公告)日：2015-08-13

申请号：US14688788

申请日：2015-04-16

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Zuozhen Fu ,  Xiaolong Ma ,  Dapeng Chen

IPC: H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Abstract translation: 公开了堆叠的纳米线MOS晶体管的制造方法。 一方面，该方法包括在基板上沿着第一方向形成多个散热片。 该方法还包括在每个翅片中形成由多个纳米线构成的纳米线堆叠。 该方法还包括在纳米线堆叠中沿着第二方向形成栅极堆叠，所述栅极堆叠围绕纳米线堆叠。 该方法还包括在栅极堆叠的两侧形成源极/漏极区域，构成沟道区域的各个源极/漏极区域之间的纳米线。 可以通过多次蚀刻形成一叠纳米线，横向蚀刻沟槽并填充沟槽。 横向蚀刻工艺包括具有内部切线和横向蚀刻的各向同性干法蚀刻，以及沿相应晶体学方向选择性蚀刻的湿蚀刻。

公开(公告)号：US20150200275A1

公开(公告)日：2015-07-16

申请号：US14585053

申请日：2014-12-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu ,  Qingqing Liang ,  Haizhou Yin

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/4925 ,  H01L29/785

Abstract: A FinFET with reduced leakage between source and drain regions, and a method for manufacturing the FinFET are disclosed. In one aspect, the method includes forming, on a semiconductor substrate, at least two openings to define a semiconductor fin. The method also includes forming a gate dielectric layer that conformally covers the fin and the openings. The method also includes forming, within the openings, a first gate conductor adjacent to the bottom of the fin. The method also includes forming, within the openings, an insulating isolation layer on the first gate conductor. The method also includes forming a second gate conductor on the fin and on the insulating isolation layer adjacent to the top of the fin. The method also includes forming spacers on sidewalls of the second gate conductor. The method also includes forming a source region and a drain region in the fin.

Abstract translation: 公开了一种在源极和漏极区域之间具有减小的漏电流的FinFET以及制造FinFET的方法。 一方面，该方法包括在半导体衬底上形成至少两个开口以限定半导体鳍片。 该方法还包括形成保形地覆盖翅片和开口的栅极电介质层。 该方法还包括在开口内形成与鳍片的底部相邻的第一栅极导体。 该方法还包括在开口内形成第一栅极导体上的绝缘隔离层。 该方法还包括在翅片上形成第二栅极导体，并且在与鳍片的顶部相邻的绝缘隔离层上形成第二栅极导体。 该方法还包括在第二栅极导体的侧壁上形成间隔物。 该方法还包括在散热片中形成源极区域和漏极区域。