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    DIRECT BULK DATA TRANSFER
    131.
    发明专利
    DIRECT BULK DATA TRANSFER 失效

    公开(公告)号：JPH09185594A

    公开(公告)日：1997-07-15

    申请号：JP30177096

    申请日：1996-11-13

    Applicant: TANDEM COMPUTERS INC

    Inventor： TOTSUDO DABURIYUU SUPURENKURU ,  SURINIBUASA DEII MAASHII ,  ANIRU KAATORI

    IPC: G06F15/16 ,  G06F9/46 ,  G06F11/20 ,  G06F15/177 ,  G06F15/163

    Abstract: PROBLEM TO BE SOLVED: To remove a similar data copy during the transfer of data between CPUs and a storage disk. SOLUTION: A storage processor 130 controls access to a server net packetizer 30 with storage devices 100 to 105, 110 to 115. A software routine is used for supplying direct access to a storage device 30 by request CPU 22. A virtual memory address to the buffer 160 of the request CPU 22 is generated by the request CPU 22. At the same time of the storage device access request, the virtual memory address is sent to CPU 20 including the storage processor 130. A working request includes the virtual memory address sent from the storage processor 130 to the storage device 30. Next data is directly transferred between request CPU 22 and the storage device 30. The storage device 30 responds to the working request next.

    ROUTE ARBITRATION METHOD FOR SHARED RESOURCE
    133.
    发明专利
    ROUTE ARBITRATION METHOD FOR SHARED RESOURCE 失效

    公开(公告)号：JPH09138774A

    公开(公告)日：1997-05-27

    申请号：JP14573496

    申请日：1996-06-07

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU JIYOERU WATOSON ,  DEIBUITSUDO POORU SOONIA

    IPC: G06F7/507 ,  G06F7/508 ,  G06F11/18 ,  G06F13/14 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  H04L12/56 ,  G06F7/50 ,  G06F15/173

    Abstract: PROBLEM TO BE SOLVED: To attain the arbitration that instantaneously uses a mechanism of high priority by monitoring the message traffic passing through every port input and elevating the priority of the port input having the message traffic under waiting. SOLUTION: A multiprocess system 10 includes at least a pair of CPUs 12a and 12b, a route designation unit, i.e., a router 16, and plural input/output units 14a to 14i which are connected to each other in a system area network constitution via a two-way communication link 18. When the two-level arbitration is carried out, the arbitration is first given between two port inputs which acquire the port input accesses by means of a low level priority mechanism. Then the port inputs having the message traffic under waiting are accepted through many arbitration cycles. Thus the priority levels of these port inputs are elevated, and the arbitration using instantaneously a high priority mechanism is applied.

    FAIL-FIRST, FAIL-FUNCTIONAL AND FAULT-TOLERANT MULTIPROCESSOR SYSTEM
    134.
    发明专利
    FAIL-FIRST, FAIL-FUNCTIONAL AND FAULT-TOLERANT MULTIPROCESSOR SYSTEM 失效

    公开(公告)号：JPH09134333A

    公开(公告)日：1997-05-20

    申请号：JP14527196

    申请日：1996-06-07

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO

    IPC: G06F12/16 ,  G06F1/04 ,  G06F11/18 ,  G06F12/08 ,  G06F15/16

    Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system via a simple system by attaining a fault tolerant action through the fail-first and fail-functional actions. SOLUTION: This clock circuit includes a binary input counter and a binary output counter and deletes the data elements out of plural storage positions of an FIFO. A clock generator supplies a clock signal of frequency F1 having an N-to-M ratio (N, M: integers and N>M) against the frequency Fo of a received clock signal. A serial shift register has plural continuous register stages to receive the clock signals from the clock generator and shifts the data bits which are received at these register stages. Then a multiplexer selectively receives one of register stages in response to a control signal and forms a sub-shift register which has plural shift registers.

    WATING-TIME SHORTENING AND ROUTE DECIDING METHODS FOR NETWORK MESSAGE ROUTE ASSIGNING DEVICE
    137.
    发明专利
    WATING-TIME SHORTENING AND ROUTE DECIDING METHODS FOR NETWORK MESSAGE ROUTE ASSIGNING DEVICE 失效

    公开(公告)号：JPH09116570A

    公开(公告)日：1997-05-02

    申请号：JP14320096

    申请日：1996-06-05

    Applicant: TANDEM COMPUTERS INC

    Inventor： JIYON SHII KURAUSU ,  UIRIAMU JIYOERU WATOSON ,  DEIBUITSUDO POORU SOONIA ,  ROBAATO DABURIYUU HOOSUTO

    IPC: G06F13/14 ,  G06F13/40 ,  H04L12/56 ,  H04L12/46 ,  H04L12/28 ,  H04L12/44 ,  H04L12/66

    Abstract: PROBLEM TO BE SOLVED: To provide a method of providing a bias to decide any of two or more inputs in contention with respect to a data communication access to the same output. SOLUTION: A designated bias value is given to each input of a router 16 allowing one communication, cumulated bias values are generated and the resulting input is compared with other inputs decided for access to its output. One of the inputs is selected for the output access based on the comparison and the cumulated bias value of the selected input is decreased by the sum of designated bias values of the other inputs participating the decision but not selected. On the other hand, each of the cumulated bias values of the other inputs taking part in the decision is increased by the designated bias value corresponding thereto. Thus, the expectation to the output access is higher for lots of the going to access the same output as they are kept waiting for a longer time, and conversely the input allowed for the access has less expectation to the access just after the allowed access in order to allow the access by the other inputs.

    COMPUTER SYSTEM WITH REMOTELY DUPLICATED AND DYNAMICALLY RECONSTITUTIBLE MEMORY
    140.
    发明专利
    COMPUTER SYSTEM WITH REMOTELY DUPLICATED AND DYNAMICALLY RECONSTITUTIBLE MEMORY 失效

    公开(公告)号：JPH0926892A

    公开(公告)日：1997-01-28

    申请号：JP10767796

    申请日：1996-04-26

    Applicant: TANDEM COMPUTERS INC

    Inventor： UIN MIN CHIYAN ,  BUAUTERU SENFU ,  TEIMOSHII SHII KEI CHIYOO ,  MAAKU EICHI RETOGARINGU ,  NUSURETSUTO YURUTOUUKU ,  KUREIGU EFU ADAMUSU

    IPC: G06F12/16 ,  G06F3/06 ,  G06F11/20

    Abstract: PROBLEM TO BE SOLVED: To completely and quickly recover from the destructions of a first- order data processing system and a related data storage device by coupling each extender of first and second cites by each single mode fiber and performing an access to a first-order disk or a mirror disk when a fiber switch goes wrong. SOLUTION: In order to simultaneously prevent the access to either one of disks from both systems, the first extender 64a of a first-order cite 10 and the third extender 64c of a second-order cide 30 or the second extender 64b of the first cite 10 and the third extender 64c of the second-order cite 30 are coupled by separate single mode fibers, respectively. For instance, when a fiber switch 62a goes wrong, the first-order cite 10 performs an access to a first-order 50 via a fourth first-order disk controller 22 and a second fiber switch 62b and performs the access to a mirror disk 52 via a third first-order disk controller 20 and a second fiber switch 63b.

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