公开(公告)号：JPH09128356A

公开(公告)日：1997-05-16

申请号：JP14527896

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  DEIBUITSUDO JIEI GAASHIA ,  UIRIAMU PATAASON BANTON ,  UIRIAMU EFU BURUTSUKAATO ,  DANIERU ERU FUAURAA ,  KAATEISU UIIRAADO JIYOONZU JIY ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  FURANKU EI UIRIAMUSU

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To add no delay to access by providing an error inspecting function and performing error inspection by an interface so that no influence is exerted on performance. SOLUTION: A data processing system 10 is equipped with two subprocessor systems 10A and 10B which have substantially the same structure and functions. Each of the subprocessor systems 10A and 10B includes a central processing unit(CPU) 12, a router 14, and plural I/O packet interfaces 16 coupled with many I/O devices 17. The pair of CPUs 12 is each equipped with an interface device. Those interface devices receive specific parts of N-bit data words from the other interface devices to which an error signal detected by miscomparison should be asserted and compare them with specific parts of N-bit data words received from the corresponding CPUs 12.

公开(公告)号：JPH09128347A

公开(公告)日：1997-05-16

申请号：JP14555196

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU EDOWAADO BEIKAA ,  RANDARU JII BANTON ,  JIYON MAIKERU BURAUN ,  UIRIAMU EFU BURUTSUKAATO ,  UIRIAMU PATAASON BANTON ,  GEARII EFU KIYANBERU ,  JIYON DEIIN KOODEINTON ,  RICHIYAADO DABURIYUU KATSUTSU ,  BARII RII DOREKUSURAA ,  HARII FURANKU ERUROTSUDO ,  DANIERU ERU FUAURAA ,  DEIBUITSUDO JIEI GAASHIA ,  POORU ENU HINTEITSUKA ,  JIEFURII AI ISUWANDEII ,  DAGURASU YUUJIIN JIYUUITSUTO ,  KAATEISU UIIRAADO JIYOONZU JIY ,  JIEEMUZU SUTEIIBUNSU KURETSUKA ,  JIYON SHII KURAUSU ,  SUTEIIBUN JII ROU ,  SUUZAN SUTOON MERADEISU ,  SUTEIIBUN SHII MEIAAZU ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  PATORISHIA ERU HOWAITOSAIDO ,  FURANKU EI UIRIAMUSU ,  RINDA ERIN ZARUZAARA

IPC: G06F11/18 ,  G06F11/16 ,  G06F15/16 ,  G06F15/17

Abstract: PROBLEM TO BE SOLVED: To facilitate fault-tolerant operation by including a routing element coupled with the central processor and peripheral device of a subprocessing system so as to transmit data between the central processor and peripheral device of the subprocessing system. SOLUTION: Subprocessor systems 10A and 10B include central processors CPUs 12, routers 14, and plural input/output I/O packet interfaces 16 connected to many I/O devices 17 by characteristic input/output NIO buses. The MPs 18 of the subprocessor system 10A and 10B connect IEEE1149. one-test buses 17 and registers used by the MPs 18 to transmit states and control information between elements and MPs 18 to elements of the subprocessor systems through on-line access port OLAP interfaces included in the elements.

公开(公告)号：JPH09244960A

公开(公告)日：1997-09-19

申请号：JP14605796

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU PATAASON BANTON ,  GEARII EFU KIYANBERU ,  RICHIYAADO DABURIYUU KATSUTSU ,  DANIERU ERU FUAURAA ,  DEIBUITSUDO JIEI GAASHIA ,  POORU ENU HINTEITSUKA ,  JIEFURII AI ISUWANDEII ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  FURANKU EI UIRIAMUSU

IPC: G06F12/14 ,  G06F11/18 ,  G06F15/16 ,  G06F15/163 ,  G06F15/167

Abstract: PROBLEM TO BE SOLVED: To check the error of a processor at an interface spot without affecting the processor performance by providing a specific table means and also a means which receives a message from a peripheral device and decides whether the access should be permitted to a memory means based on the received message. SOLUTION: The routers 14A and 14B are connected to the subprocessor systems 10A and 10B, and the I/O packets 16A and 16B are connected to the routers 14A and 14B respectively. This device of such a constitution has a table means which includes plural entries to discriminate permission of the access to a part of a memory means against one of its peripheral devices. Therefore, the message packet sent via an I/O has the information on the originator and the destination. Then a receiving CPU refers to the external source that is permitted to access its memory via an access propriety check and a conversion (AVT) table and checks whether the access is permitted or not.

公开(公告)号：JPH09134336A

公开(公告)日：1997-05-20

申请号：JP14527096

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU EDOWAADO BEIKAA ,  RINDA ERIN ZARUZAARA ,  UIRIAMU PATAASON BANTON ,  RICHIYAADO DABURIYUU KATSUTSU ,  DEIBUITSUDO JIEI GAASHIA ,  JIYON SHII KURAUSU ,  SUTEIIBUN JII ROU ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  PATORISHIA ERU HOWAITOSAIDO

IPC: G06F11/18 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  H04L1/24 ,  H04L9/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system via a single system by attaining a fault tolerant action through the fail-first and fail-functional actions. SOLUTION: The transmitting clock signals existing on a two-way link are supplied to a pair of transmitting and receiving elements in order to demarcate the clock cycles and also to receive the multi-bit words in a processing system which includes the paired transmitting and receiving elements connected to each other for communication of the multi-bit words including the multi-bit data words and multi-bit command words. Then one of paired transmitting and receiving elements transmits the data to the other element in form of a series of multi-bit data words, transmits the multi-bit data words in every clock cycle and transmits the multi-bit command words in every clock cycle and with no sequence.

公开(公告)号：JPH09244906A

公开(公告)日：1997-09-19

申请号：JP14555296

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： JIEFURII AI ISUWANDEII ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU PATAASON BANTON ,  JIYON DEIIN KOODEINTON ,  DANIERU ERU FUAURAA ,  DEIBUITSUDO JIEI GAASHIA ,  POORU ENU HINTEITSUKA ,  SUUZAN SUTOON MERADEISU ,  SUTEIIBUN EICHI MIRAA ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  FURANKU EI UIRIAMUSU

IPC: G06F13/14 ,  G06F9/46 ,  G06F9/48 ,  G06F11/18 ,  G06F13/24 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To execute the error check of a processor so as not to affect performance at the spot of an interface. SOLUTION: Routers 14A and 14B are connected to sub processor systems 10A and 10B which are one duplex pair of this multiprocessor system and I/O packet interfaces 16A and 16B are connected to the routers. Message packets are copied by the routers and sent by a method for ensuring the synchronization of the both of the pair. Since interruption issued from an I/O element is provided with the information of the cause of the interruption and transmitted by the message packet similarly to other information transfer, protection by the CRC(cyclic redundancy check) of the interruption is performed and the need of deciding the cause from a CPU side is eliminated. The message packet sent through the I/O is provided with the information of an originator and a destination and a reception CPU refers to an external source for permitting access to the memory by an access propriety check and conversion (AVT) chart and checks whether or not the access is allowed.

公开(公告)号：JPH09134337A

公开(公告)日：1997-05-20

申请号：JP14605596

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： JIYON SHII KURAUSU ,  DEIBUITSUDO JIEI GAASHIA ,  ROBAATO DABURIYUU HOOSUTO ,  JIEFURII AI ISUWANDEII ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  RINDA ERIN ZARUZAARA

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system via a single system by attaining a fault tolerant action through the fail-first and fail-functional actions. SOLUTION: The digital information are communicated among plural processing system elements in the form of a message packet which includes the data to identify these system elements as addresses. Then plural port means of an input/output routing device correspond to the processing system elements and transmit and receive in 2-way fashion the message packet to each other. Furthermore, the routing means answers the address identification data, checks the message packet and sends an error mark to the message packet if an error is detected in order to select one of those port means which are connected together so as to enable a processing system element to send the message packet to another.

公开(公告)号：JPH09128353A

公开(公告)日：1997-05-16

申请号：JP14605696

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： DEIBUITSUDO POORU SOONIA ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU PATAASON BANTON ,  JIYON SHII KURAUSU ,  KENISU EICHI POOTAA ,  UIRIAMU JIYOERU WATOSON ,  RINDA ERIN ZARUZAARA

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To reduce the processing system cost by providing an error inspecting function and masking a fault through hardware in duplex mode operation. SOLUTION: A data processing system 10 is equipped with two subprocessor systems 10A and 10B which have the same constitution and functions. This pair of the subprocessor systems 10A and 10B include a processor device (CPU) 12, a router 14, and an I/O packet interface 16 having a relative I/O device 17. Each of the pair of the CPUs 12 receive an error signal and returns an echo-back error signal to a couple of data communication elements. Then it is determined whether or not each CPU 12 continues to operate according to the error signal and echo-back error signal; and then one of the CPUs 12 continues to operate and the other CPU 12 finishes operating.

公开(公告)号：JPH09138774A

公开(公告)日：1997-05-27

申请号：JP14573496

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU JIYOERU WATOSON ,  DEIBUITSUDO POORU SOONIA

IPC: G06F7/507 ,  G06F7/508 ,  G06F11/18 ,  G06F13/14 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  H04L12/56 ,  G06F7/50 ,  G06F15/173

Abstract: PROBLEM TO BE SOLVED: To attain the arbitration that instantaneously uses a mechanism of high priority by monitoring the message traffic passing through every port input and elevating the priority of the port input having the message traffic under waiting. SOLUTION: A multiprocess system 10 includes at least a pair of CPUs 12a and 12b, a route designation unit, i.e., a router 16, and plural input/output units 14a to 14i which are connected to each other in a system area network constitution via a two-way communication link 18. When the two-level arbitration is carried out, the arbitration is first given between two port inputs which acquire the port input accesses by means of a low level priority mechanism. Then the port inputs having the message traffic under waiting are accepted through many arbitration cycles. Thus the priority levels of these port inputs are elevated, and the arbitration using instantaneously a high priority mechanism is applied.

公开(公告)号：JPH09128348A

公开(公告)日：1997-05-16

申请号：JP14524996

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： DEIBUITSUDO POORU SOONIA ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU PATAASON BANTON ,  DANIERU ERU FUAURAA ,  KAATEISU UIIRAADO JIYOONZU JIY ,  JIYON SHII KURAUSU ,  MAIKERU PII SHINPUSON ,  UIRIAMU JIYOERU WATOSON

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To facilitate fault-tolerant operation by establishing synchronized and substantially lock-step operation of a 2nd processor element by a 1st processor element which should have the 2nd processor element executing the same instruction at substantially the same moment with the 1st processor element. SOLUTION: A frequency confinement clock signal is used to sent symbols between CPUs 12 of subprocessor systems 10A and 10B paired with routers 14A and 14B. Each route 14 is equipped with six two-way TNet ports 0-5. Two ports 4 and 5 used to connect to the CPU 12 are constituted differently to some extent. This difference enables operation in synchronized lock step mode. For example, a message packet received by the port 3 of the route 14A, for example, is copied by the router 14A and sent from the routers 4 and 5 so that the same symbol is transmitted to the CPU 12 at substantially the same time.

公开(公告)号：JPH09116570A

公开(公告)日：1997-05-02

申请号：JP14320096

申请日：1996-06-05

Applicant: TANDEM COMPUTERS INC

Inventor： JIYON SHII KURAUSU ,  UIRIAMU JIYOERU WATOSON ,  DEIBUITSUDO POORU SOONIA ,  ROBAATO DABURIYUU HOOSUTO

IPC: G06F13/14 ,  G06F13/40 ,  H04L12/56 ,  H04L12/46 ,  H04L12/28 ,  H04L12/44 ,  H04L12/66

Abstract: PROBLEM TO BE SOLVED: To provide a method of providing a bias to decide any of two or more inputs in contention with respect to a data communication access to the same output. SOLUTION: A designated bias value is given to each input of a router 16 allowing one communication, cumulated bias values are generated and the resulting input is compared with other inputs decided for access to its output. One of the inputs is selected for the output access based on the comparison and the cumulated bias value of the selected input is decreased by the sum of designated bias values of the other inputs participating the decision but not selected. On the other hand, each of the cumulated bias values of the other inputs taking part in the decision is increased by the designated bias value corresponding thereto. Thus, the expectation to the output access is higher for lots of the going to access the same output as they are kept waiting for a longer time, and conversely the input allowed for the access has less expectation to the access just after the allowed access in order to allow the access by the other inputs.