公开(公告)号：KR100493850B1

公开(公告)日：2005-08-29

申请号：KR1019980026953

申请日：1998-07-04

Applicant: 삼성전자주식회사

Inventor： 심광보 ,  이영우 ,  김태룡 ,  박재현

IPC: H01L21/3205

Abstract: 본 발명은 반도체소자의 금속막 형성방법에 관한 것이다.
본 발명의 반도체소자의 금속막 형성방법은, 반도체기판 상에 제1절연막을 형성시킨 후, 상감기법의 프로파일을 가지는 패턴 등이 형성되도록 상기 제1절연막을 제거시키는 단계; 상기 상감기법의 프로파일을 가지는 패턴을 포함하는 절연막의 표면으로 경계금속막을 형성시킨 후, 그 상부에 금속막을 형성시키는 단계; 상기 금속막 상에 제2절연막을 형성시킨 후, 상기 금속막이 노출되도록 상기 제2절연막을 에치백시키는 단계; 및 상기 제1절연막 상의 경계금속막이 노출되도록 상기 금속막을 에치백시키는 단계를 구비하여 이루어짐을 특징으로 한다.
따라서, 에치백을 이용한 콘택홀 또는 상감기법의 프로파일을 가지는 패턴 내의 금속막의 형성시 발생하는 불량을 최소화시켜 반도체소자의 신뢰도를 향상시킬 수 있고, 또한 기존의 식각장치를 활용할 수 있는 효과가 있다.

公开(公告)号：KR1020050049810A

公开(公告)日：2005-05-27

申请号：KR1020030083551

申请日：2003-11-24

Applicant: 삼성전자주식회사

Inventor： 정원철 ,  김형준 ,  박재현 ,  정창욱

IPC: H01L27/108

CPC classification number: H01L45/06 ,  H01L45/122 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1666

Abstract: 본 발명은 상변화 기억 소자 및 그 형성방법을 제공한다. 이 소자는 전극홀을 갖는 가열 전극을 갖는다. 전극홀은 가열 전극의 소정영역을 관통한다. 상변화 물질 패턴이 전극홀의 내측벽과 접촉한다. 이에 따라, 가열 전극과 상변화 물질 패턴의 접촉면적을 감소시켜 상변화 기억 소자의 소비 전력을 감소시킬 수 있다.

公开(公告)号：KR1020050030741A

公开(公告)日：2005-03-31

申请号：KR1020030066826

申请日：2003-09-26

Applicant: 삼성전자주식회사

Inventor： 윤인구 ,  유재민 ,  박재현 ,  이용선 ,  문정호

IPC: H01L27/115

Abstract: A split-gate type non-volatile memory device is provided to increase the voltage induced to a floating gate and improve a program characteristic by additionally forming the planarized second insulation layer on the first insulation layer. A semiconductor substrate(200) is prepared. A gate insulation layer pattern(230) is formed on the semiconductor substrate. A floating gate pattern(240) which is thinner in its center portion than both its edge portions is formed on the gate insulation layer pattern. An interpoly dielectric(270) is formed on the floating gate pattern, including the first and second insulation layers(250,260). The first insulation layer is thinner in both its edge portions than its center portion, The second insulation layer which is thicker in its center portion than both its edge portions to make the upper surface flat is formed on the first insulation layer. One sidewall of the resultant structure and the upper surface of the semiconductor substrate adjacent to the one sidewall are covered with a tunnel insulation layer pattern(290). A control gate pattern(300) is formed on the tunnel insulation layer pattern.

Abstract translation: 分离栅型非易失性存储器件被提供以通过在第一绝缘层上另外形成平坦化的第二绝缘层来增加感应到浮动栅极的电压并改善程序特性。 制备半导体衬底（200）。 在半导体衬底上形成栅极绝缘层图案（230）。 在栅极绝缘层图案上形成有比其两个边缘部分在其中心部分更薄的浮栅图案（240）。 在浮栅图案上形成多层电介质（270），包括第一和第二绝缘层（250,260）。 第一绝缘层在其边缘部分比其中心部分更薄。在第一绝缘层上形成有在其中心部分比其两个边缘部分更厚以使上表面平坦的第二绝缘层。 所得结构的一个侧壁和与一个侧壁相邻的半导体衬底的上表面被隧道绝缘层图案（290）覆盖。 在隧道绝缘层图案上形成控制栅极图案（300）。

公开(公告)号：KR1020040036405A

公开(公告)日：2004-04-30

申请号：KR1020020065425

申请日：2002-10-25

Applicant: 삼성전자주식회사

Inventor： 김태동 ,  박재현

IPC: G01C9/18

Abstract: PURPOSE: A level measurement apparatus is provided to prevent a fault during a semiconductor manufacturing process by precisely measuring a level of semiconductor manufacturing equipment. CONSTITUTION: A level measurement apparatus(180a) mainly includes a tube(100) containing first and second fluids(120,140) therein, and a position checking line(160) for checking a movement of second fluid(140) contained in the tube(100). The tube(100) has a ring shape and an upper surface of the tube(100) has a semi-spherical shape. The tube(100) is made from soft transparent material. The first fluid(120) has high viscosity and specific gravity. The second fluid(140) is preferably made from material, which is not dissolved in the first fluid(120).

Abstract translation: 目的：提供一种电平测量装置，通过精确测量半导体制造设备的水平来防止半导体制造过程中的故障。 构成：水平测量装置（180a）主要包括容纳第一和第二流体（120,140）的管（100）和用于检查包含在管（100）中的第二流体（140）的运动的位置检查线（160） ）。 管（100）具有环形，并且管（100）的上表面具有半球形形状。 管（100）由柔软的透明材料制成。 第一流体（120）具有高粘度和比重。 第二流体（140）优选由不溶解在第一流体（120）中的材料制成。

公开(公告)号：KR100424657B1

公开(公告)日：2004-03-24

申请号：KR1020010041939

申请日：2001-07-12

Applicant: 삼성전자주식회사

Inventor： 고동환 ,  윤석훈 ,  박재현

IPC: H01L21/82

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a fuse pattern for repairing a bad cell includes forming a metal wiring pattern on a substrate and successively forming an insulating layer on the metal wiring pattern and the substrate. The insulating layer of a region for defining the fuse pattern is etched by using an etching gas including a fluorocarbon-type compound and a fluorosilicate-type compound, which substantially suppresses a generation of by-products. A partially exposed metal layer of the metal wiring pattern is removed to form a fuse. Accordingly, a structure such as a fence is not formed on the residue of insulating layer. Therefore, the removal process for the fence is unnecessary. As a result, the process for forming the fuse is simplified.

Abstract translation: 一种形成用于修复坏单元的熔丝图案的方法包括在基片上形成金属布线图案并在金属布线图案和基片上依次形成绝缘层。 通过使用包含氟碳化合物和氟硅酸盐型化合物的蚀刻气体来蚀刻用于限定熔丝图案的区域的绝缘层，这基本上抑制了副产物的产生。 金属布线图案的部分暴露的金属层被去除以形成熔丝。 因此，在绝缘层的残留物上不形成诸如栅栏的结构。 因此，栅栏的移除过程是不必要的。 结果，形成熔丝的过程得以简化。

公开(公告)号：KR1020000066421A

公开(公告)日：2000-11-15

申请号：KR1019990013504

申请日：1999-04-16

Applicant: 삼성전자주식회사

Inventor： 고동환 ,  박재현 ,  백재학

IPC: H01L21/32

Abstract: PURPOSE: A method for manufacturing a semiconductor fine pattern is provided to stably etch the fine pattern when a polymer spacer is used as an etching mask, by hardening the polymer spacer using an ion injection. CONSTITUTION: A photoresist pattern(52) is formed on a specific layer. A part of the photoresist pattern is etched to form a polymer spacer(53) on a sidewall. An ion injection is performed regarding the photoresist pattern and polymer spacer. The specific layer is etched to form a fine pattern by using the photoresist pattern and polymer spacer as a mask.

Abstract translation: 目的：提供一种用于制造半导体精细图案的方法，通过使用离子注入对聚合物间隔物进行硬化，以使用聚合物间隔物作为蚀刻掩模来稳定蚀刻精细图案。 构成：在特定层上形成光致抗蚀剂图案（52）。 蚀刻光致抗蚀剂图案的一部分以在侧壁上形成聚合物间隔物（53）。 对光致抗蚀剂图案和聚合物间隔物进行离子注入。 通过使用光致抗蚀剂图案和聚合物间隔物作为掩模来蚀刻特定层以形成精细图案。

公开(公告)号：KR1020000026911A

公开(公告)日：2000-05-15

申请号：KR1019980044657

申请日：1998-10-23

Applicant: 삼성전자주식회사

Inventor： 김성환 ,  김태룡 ,  박재현 ,  정민제

IPC: H01L27/108

Abstract: PURPOSE: A method for manufacturing memory capacitor is provided to simplify manufacturing processes and improve a step coverage by surrounding an upper part and side walls of bit line with an insulating material having a high selectivity,compared to an interlayer dielectric. CONSTITUTION: A memory capacitor includes a contact pad(106) connected to a substrate(100) through a first interlayer dielectric(104). Bit line bodies(111) having bit lines(108) are surrounded by insulating layers(107,109,110) on the first interlayer dielectrics(104) of both sides of the contact pad(106). A second interlayer dielectric is formed on the resultant structure, wherein the insulating layers(109,110) are made of silicon nitride having high etching selectivity compared to the second interlayer dielectric made of silicon oxide and used as an etching stopper. An opening used for a lower electrode of a capacitor is formed by partially etching the second interlayer dielectric to expose the upper surface of the contact pad(106). A storage electrode(118a) connected to the contact pad(106) is formed by filling the opening with a conductive layer.

Abstract translation: 目的：提供一种用于制造记忆电容器的方法，以便与层间电介质相比，通过用具有高选择性的绝缘材料围绕位线的上部和侧壁来简化制造工艺并提高阶梯覆盖。 构成：存储电容器包括通过第一层间电介质（104）连接到衬底（100）的接触焊盘（106）。 具有位线（108）的位线体（111）被接触焊盘（106）两侧的第一层间电介质（104）上的绝缘层（107,109,110）包围。 在所得结构上形成第二层间电介质，其中绝缘层（109,110）由与氧化硅制成的第二层间电介质相比具有高蚀刻选择性的氮化硅制成并用作蚀刻停止层。 通过部分地蚀刻第二层间电介质以暴露接触焊盘（106）的上表面，形成用于电容器的下电极的开口。 通过用导电层填充开口来形成连接到接触焊盘（106）的存储电极（118a）。

公开(公告)号：KR1020000026750A

公开(公告)日：2000-05-15

申请号：KR1019980044412

申请日：1998-10-22

Applicant: 삼성전자주식회사

Inventor： 김성환 ,  박재현 ,  심광보 ,  정민제

IPC: H01L21/203

Abstract: PURPOSE: A new type of sputter having a holder with an inclination of 3-9 degrees enables metals to be evaporated uniformally on the wafer. CONSTITUTION: A sputter(10) evaporates atoms springing straightly out of a metal target(14)on a wafer(30). At the early stage of evaporation, the wafer(30) is placed horizontally against the holder(20), and a spin motor(24) is operated by a controller(26). Thus, a supporting axis(22) and the wafer(30) rotate, also metal atoms are evaporated uniformally on the side(31a) of the contact hole(32).

Abstract translation: 目的：具有3-9度倾斜度的保持器的新型溅射使金属在晶片上均匀蒸发。 构成：溅射（10）蒸发直接从晶片（30）上的金属靶（14）弹出的原子。 在蒸发的早期阶段，将晶片（30）水平地放置在保持器（20）上，并通过控制器（26）操作旋转电动机（24）。 因此，支撑轴（22）和晶片（30）旋转，金属原子在接触孔（32）的侧面（31a）上均匀蒸发。

公开(公告)号：KR1020000010248A

公开(公告)日：2000-02-15

申请号：KR1019980031090

申请日：1998-07-31

Applicant: 삼성전자주식회사

Inventor： 박재현

IPC: H04M11/02

Abstract: PURPOSE: A tone frequency generator capable of exactly generating a tone frequency corresponding to each button according to a programmed frequency information signal of each button is provided. CONSTITUTION: The tone frequency generator comprising: a microcomputer(10) for outputting a tone counter signal(TC), a tone selecting signal(TS), a tone frequency number signal(TF); a tone counter(20) for counting an input frequency clock corresponding to a tone counter signal(TC) from the microcomputer(10), outputting a counting signal, and being reset and again performing a counting operation; a duty generator(30) for outputting a toggle signal which toggles the output signal of the tone counter(20); a tone frequency number generator(40) for receiving the output signal of the duty generator(30) by a frequency number corresponding to the tone frequency number signal from the microcomputer(10) and outputting a complete signal; and a tone select signal generator(50) for controlling operations of the tone counter(20), duty generator(30), and tone frequency number generator(40) according to the tone selecting signal from the microcomputer(10), and resetting the microcomputer(10), tone counter(20), duty generator(30), and tone frequency number generator(40) according to the complete signal from the tone frequency number generator(40).

Abstract translation: 目的：提供能够根据每个按钮的编程频率信息信号精确地产生与每个按钮对应的音频的音频发生器。 音调频率发生器，包括：用于输出音调计数器信号（TC）的微型计算机（10），音调选择信号（TS），音调频率信号（TF）; 用于对来自微型计算机（10）的音调计数器信号（TC）的输入频率时钟进行计数的计数器（20），输出计数信号，并重新进行计数操作; 用于输出切换音调计数器（20）的输出信号的触发信号的占空比发生器（30）; 用于通过与来自微计算机（10）的音调频率信号相对应的频率号接收占空比发生器（30）的输出信号并输出​​完整信号的音频数字发生器（40） 以及根据来自微计算机（10）的音调选择信号，控制音调计数器（20），占空比发生器（30）和音频数量发生器（40）的操作的音调选择信号发生器（50） 微计算机（10），音调计数器（20），占空比发生器（30）和音调频率数发生器（40）。

公开(公告)号：KR1020000007552A

公开(公告)日：2000-02-07

申请号：KR1019980026953

申请日：1998-07-04

Applicant: 삼성전자주식회사

Inventor： 심광보 ,  이영우 ,  김태룡 ,  박재현

IPC: H01L21/3205

Abstract: PURPOSE: A forming method of a metal layer is provided to improve reliability of semiconductor devices by minimizing defects generated while forming the metal layer in a pattern having a contact hole or an inlay profile. CONSTITUTION: The method comprises the steps of forming a first insulating layer on a semiconductor substrate; removing the first insulating layer to form a pattern having the inlay profile; forming an interface metal layer on a surface of the insulating layer including the pattern having the inlay profile; forming a metal layer on the interface metal layer; forming a second insulating layer on the metal layer; etching back the second insulating layer to expose the metal layer; and etching back the metal layer to expose the interface metal layer on the first insulating layer.

Abstract translation: 目的：提供金属层的形成方法，以通过使形成具有接触孔或镶嵌轮廓的图案中的金属层所产生的缺陷最小化来提高半导体器件的可靠性。 构成：该方法包括以下步骤：在半导体衬底上形成第一绝缘层; 去除第一绝缘层以形成具有嵌体轮廓的图案; 在包括具有嵌体轮廓的图案的绝缘层的表面上形成界面金属层; 在界面金属层上形成金属层; 在所述金属层上形成第二绝缘层; 蚀刻第二绝缘层以暴露金属层; 并蚀刻回金属层以暴露第一绝缘层上的界面金属层。