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公开(公告)号：KR101283686B1
公开(公告)日：2013-07-08
申请号：KR1020090111657
申请日：2009-11-18
Applicant: 한국전자통신연구원 , 주식회사 나노신소재
IPC: H01B1/22 , H01B1/02 , H01L21/203
Abstract: 본 발명은 열안정성 투명 도전막 및 투명 도전막의 제조방법에 관한 것이다. 본 발명에 따른 투명 도전막은 산화인듐 및 산화주석에 티타늄을 포함시킴으로써 비교적 낮은 온도에서의 열처리에도 결정화되고, 안정적인 비저항값을 가져 열안정성을 이룰 수 있다.
열안정성, 투명, 도전막, 티타늄-
公开(公告)号：KR1020130074954A
公开(公告)日：2013-07-05
申请号：KR1020110143098
申请日：2011-12-27
Applicant: 한국전자통신연구원
IPC: H01L29/786 , H01L21/336
CPC classification number: H01L29/7827 , H01L29/41733 , H01L29/78642 , H01L29/78696
Abstract: PURPOSE: A vertical channel thin film transistor is provided to minimize a leakage current and capacitance by minimizing an overlap area between a source electrode and a drain electrode. CONSTITUTION: A drain electrode (220) is formed on the upper part of a substrate (210). A spacer (230) is formed on the upper side of the substrate in contact with the drain electrode. A source electrode (240) is formed on the upper side of the spacer. An active layer (250) is formed on the front surface of the substrate including the drain electrode and the source electrode. A gate insulation layer (260) is formed on the upper side of the active layer. A gate electrode (270) is formed on the upper side of the gate insulation layer.
Abstract translation: 目的：提供垂直沟道薄膜晶体管，通过最小化源电极和漏电极之间的重叠面积来最小化泄漏电流和电容。 构成：在基板（210）的上部形成漏电极（220）。 在与漏电极接触的基板的上侧形成间隔物（230）。 源极电极（240）形成在间隔物的上侧。 在包括漏电极和源电极的基板的前表面上形成有源层（250）。 栅极绝缘层（260）形成在有源层的上侧。 在栅极绝缘层的上侧形成有栅电极（270）。
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公开(公告)号：KR1020130040994A
公开(公告)日：2013-04-24
申请号：KR1020130025813
申请日：2013-03-11
Applicant: 한국전자통신연구원 , 한양대학교 산학협력단
IPC: H03K19/0185 , G09G3/20 , G09G3/36
CPC classification number: H03K19/018521 , G09G3/3677 , G09G2310/0289 , H03K3/356113
Abstract: PURPOSE: A level shifter and a scan driving circuit including the same are provided to embed within a display panel and to have small power consumption and to be capable of full swing using an oxide thin film transistor. CONSTITUTION: A level shifter includes a pull down unit(300A) consisting of a plurality of n-type oxide thin film transistors pull downing an output signal to ground voltage according to a non-inverting input signal, a pull up unit(300B) consisting of a plurality of n-type oxide thin film transistors pulling up an output signal to power supply voltage according to an inverting input signal; and the plurality of n-type oxide thin film transistors comprising the pull up unit are connected in a latch structure and pull up an output signal to power supply voltage.
Abstract translation: 目的：提供一种电平移位器和包括该电平移位器和扫描驱动电路以嵌入显示面板内并具有小功率消耗并能够使用氧化物薄膜晶体管全摆动。 构成：电平移位器包括由多个n型氧化物薄膜晶体管组成的下拉单元（300A），该n型氧化物薄膜晶体管根据非反相输入信号将输出信号下拉至接地电压，上拉单元（300B） 多个n型氧化物薄膜晶体管，根据反相输入信号将输出信号提升到电源电压; 并且包括上拉单元的多个n型氧化物薄膜晶体管以闩锁结构连接并将输出信号上拉到电源电压。
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公开(公告)号：KR101220451B1
公开(公告)日：2013-01-10
申请号：KR1020090090026
申请日：2009-09-23
Applicant: 한국전자통신연구원 , 한양대학교 산학협력단
Abstract: 본 발명에 따르면 산화물 박막 트랜지스터를 이용하여 디스플레이 패널에 내장이 가능하면서 양전압과 음전압을 제공할 수 있는 고효율의 DC-DC 컨버터를 구현할 수 있으므로, 디스플레이 구동 장치의 소형화 및 제조 비용의 감소를 도모할 수 있다.
DC-DC, 디스플레이, 구동, 산화물 박막 트랜지스터-
公开(公告)号：KR1020120129670A
公开(公告)日：2012-11-28
申请号：KR1020110048064
申请日：2011-05-20
Applicant: 한국전자통신연구원
IPC: G06F17/50 , G06F17/10 , H01L29/772
CPC classification number: G06F17/5036 , G06F17/10 , G06F17/5045 , H01L29/772
Abstract: PURPOSE: A method and an apparatus of modeling a transistor are provided to model a drain current value of a transistor by applying modeling variables to a drain current modeling function. CONSTITUTION: A reference mobility value of a channel layer of a transistor is extracted by using a reference gate voltage value and a reference drain current value(S20). A modeling variable is extracted by fitting a mobility function to a mobility value(S30). The modeling variable is applied to a drain current modeling function to calculate a drain current value(S40). [Reference numerals] (AA) Start; (BB) End; (S10) Measuring a reference drain current value by applying a reference gate voltage value and a reference drain voltage value; (S20) Extracting reference mobility values by using the reference gate voltage value and the reference drain current value; (S30) Extracting modeling variables by fitting a mobility function to the reference mobility values; (S40) Drain current modeling
Abstract translation: 目的：提供一种对晶体管进行建模的方法和装置，以通过将建模变量应用于漏极电流建模功能来建模晶体管的漏极电流值。 构成：通过使用参考栅极电压值和参考漏极电流值来提取晶体管的沟道层的参考迁移率值（S20）。 通过将移动性函数拟合为移动性值来提取建模变量（S30）。 建模变量应用于漏极电流建模功能以计算漏极电流值（S40）。 （附图标记）（AA）开始; （BB）结束; （S10）通过施加基准栅极电压值和基准漏极电压值来测量参考漏极电流值; （S20）使用参考栅极电压值和参考漏极电流值提取参考迁移率值; （S30）通过将移动性函数拟合为参考迁移率值来提取建模变量; （S40）排水电流建模
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Patent Agency Ranking
公开(公告)号：KR1020120127166A
公开(公告)日：2012-11-21
申请号：KR1020110094568
申请日：2011-09-20
Applicant: 한국전자통신연구원
IPC: H01L29/786 , H01L21/336
CPC classification number: H01L29/7869 , H01L29/66742 , H01L29/78606
Abstract: PURPOSE: An oxide thin film transistor and a manufacturing method thereof are provided to improve reliability of a photovoltage by forming a diffusion preventing layer which prevents a hole and an ionized oxygen vacancy from moving in a low temperature of 50°C-200°C. CONSTITUTION: A gate electrode(20) is formed on a substrate(10). A gate insulating layer(30) is formed on the upper side of the substrate including the gate electrode. A source electrode(40a) and a drain electrode(40b) are formed on both sides of the gate insulating layer. An active layer(50) and a protective layer(60) are formed on the top of the substrate including a part of the drain electrode and the source electrode. The active layer comprises an oxide semiconductor and a diffusion preventing layer.
Abstract translation: 目的：提供一种氧化物薄膜晶体管及其制造方法，以通过形成防止空穴和电离氧空位在50℃-200℃的低温下移动的扩散防止层来提高光电压的可靠性。 构成：在基板（10）上形成栅电极（20）。 在包括栅电极的基板的上侧形成栅极绝缘层（30）。 源极电极（40a）和漏电极（40b）形成在栅极绝缘层的两侧。 在包括漏电极和源电极的一部分的衬底的顶部上形成有源层（50）和保护层（60）。 有源层包括氧化物半导体和扩散防止层。
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公开(公告)号：KR1020120108894A
公开(公告)日：2012-10-05
申请号：KR1020110085561
申请日：2011-08-26
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
IPC: H03K19/094 , H03K19/20
CPC classification number: H03K19/094 , H03K19/00 , H03K19/02 , H03K19/08 , H03K19/20
Abstract: PURPOSE: An inverter, an NAND gate, and an NOR gate are provided to provide a digital logic gate driven in low consumption power equal to power in a CMOS(Complementary Metal-Oxide Semiconductor) circuit by controlling the flow of a current according to an input and output signal. CONSTITUTION: An inverter comprises a pull-up part(210), a pull down part(220), and a pull up drive part(230). The pull-up part is composed of a second TFT(Thin Film Transistor) outputting a first power supply voltage to an output terminal according to a voltage applied to a gate. The pull down part is composed of a fifth TFT outputting a ground voltage to the output terminal according to the input signal voltage applied to the gate. The pull up drive part applies a second power supply voltage or the ground voltage to the gage in a second TFT according to the input signal.
Abstract translation: 目的：提供一个反相器，一个与非门和一个或非门，以通过控制电流的流动来提供在CMOS（互补金属氧化物半导体）电路中等于功率的低功耗驱动的数字逻辑门 输入和输出信号。 构成：逆变器包括上拉部分（210），下拉部分（220）和上拉驱动部分（230）。 上拉部分由根据施加到栅极的电压将第一电源电压输出到输出端的第二TFT（薄膜晶体管）组成。 下拉部分由根据施加到栅极的输入信号电压向输出端输出接地电压的第五TFT组成。 上拉驱动部件根据输入信号将第二电源电压或接地电压施加到第二TFT中的量规。
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公开(公告)号：KR101182403B1
公开(公告)日：2012-09-13
申请号：KR1020080131647
申请日：2008-12-22
Applicant: 한국전자통신연구원
IPC: H01L29/786
CPC classification number: H01L29/66742 , H01L29/45 , H01L29/4908 , H01L29/786 , H01L29/7869
Abstract: 본 발명에 따른 투명 트랜지스터는 기판, 하부 투명층, 금속층 및 상부 투명층의 다층 구조를 가지며, 상기 기판 위에 형성되어 있는 소스 전극 및 드레인 전극, 상기 소스 전극 및 드레인 전극 사이에 형성되어 있는 채널, 그리고 상기 채널과 정렬되어 있는 게이트 전극을 포함하며, 상기 하부 투명층 또는 상부 투명층이 상기 채널과 동일한 투명 반도체층으로 형성되어 있다. 따라서, 다층 투명전도막을 활용하여 투명도 및 전도도를 확보하면서, 소스/드레인 전극과 반도체의 접촉 저항 문제를 해결하고, 박막 증착 시에 추가되는 공정에 비하여 패터닝 공정의 감소로 공정의 효율성이 높아질 수 있다.
투명 소자, 투명 트랜지스터, 투명 전도막-
公开(公告)号：KR1020120062341A
公开(公告)日：2012-06-14
申请号：KR1020100123561
申请日：2010-12-06
Applicant: 한국전자통신연구원
CPC classification number: C23C14/3414 , C23C14/086
Abstract: PURPOSE: An IZO(Indium Zinc Oxide) transparent conductive film and a manufacturing method thereof are provided to obtain a thin film with enhanced etching properties and to obtain an amorphous or nano crystalline thin film at low temperatures. CONSTITUTION: An IZO transparent conductive film comprises indium oxide, zinc oxide, and titanium oxide. The IZO transparent conductive film is formed from an IZO sputtering target expressed as the following formula, InxZny(TiO2-a)z, where x+y
Abstract translation: 目的：提供IZO（氧化铟锌）透明导电膜及其制造方法以获得具有增强的蚀刻性能的薄膜，并在低温下获得非晶或纳米晶体薄膜。 构成：IZO透明导电膜包括氧化铟，氧化锌和氧化钛。 IZO透明导电膜由下式表示的IZO溅射靶InxZny（TiO2-a）z形成，其中x + y <= 1，0.0001 <= z <0.002，x：y = 8.5-9.5:1.5 -0.5和0.5 <= a <= 1。
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公开(公告)号：KR1020120055173A
公开(公告)日：2012-05-31
申请号：KR1020100116736
申请日：2010-11-23
Applicant: 한국전자통신연구원
IPC: G11C11/22
CPC classification number: G11C11/22 , G11C7/10 , G11C7/22 , G11C11/223 , G11C11/2273 , G11C11/2275
Abstract: PURPOSE: A memory cell and a memory device using the same are provided to improve stability by preventing an electrode from being floated in a memory array area. CONSTITUTION: A ferroelectric transistor(110) is provided. A plurality of switching devices(111,112,113) are electrically combined with the ferroelectric transistor. A plurality of control lines transmit each control signal for controlling a plurality of switching device to each switching device. The plurality of switching devices are individually controlled based on each control signal to prevent each electrode of the ferroelectric transistor from being floated.
Abstract translation: 目的：提供一种存储单元和使用其的存储器件，以通过防止电极浮在存储器阵列区域来提高稳定性。 构成：提供铁电晶体管（110）。 多个开关器件（111,112,113）与铁电晶体管电气组合。 多个控制线将用于控制多个开关装置的每个控制信号发送到每个开关装置。 基于每个控制信号单独地控制多个开关装置，以防止铁电晶体管的每个电极浮动。
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