IMAGE PICKUP CIRCUIT AND SPATIAL COMPENSATION METHOD

    公开(公告)号:JP2000032351A

    公开(公告)日:2000-01-28

    申请号:JP15104099

    申请日:1999-05-31

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide an improved image pickup system capable of compensating different responses to light rays at the different areas of an optical sensor. SOLUTION: In this image pickup system 10, the different amplitudes of pixel signals generated by optical active elements in the optical sensor 32 whose response to projected light is not uniform are compensated. The sensor is divided into area groups 52 so as to practically equalize the responses of optical active elements in the area. When the pixel signals generated in different areas are received, a processing circuit 34 compensates the different responses at the different area through a programmable gain amplifier 72 for dynamically controlling the gain.

    HOUSING ASSEMBLY FOR PORTABLE RADIO TELEPHONE

    公开(公告)号:JP2000031655A

    公开(公告)日:2000-01-28

    申请号:JP13343599

    申请日:1999-05-14

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To ensure rigid fitting by composing a housing assembly of first and second housings for limiting outer circumferential movement of first fitting outer circumference which has a tab and second fitting outer circumference having a slot. SOLUTION: Rear face housing part 106 forms a housing shell having an outer surface 302, an inner surface 304 and a fitting outer circumference 306 extending along the wall of the housing shell. The back housing part 106 is provided with at least a first tab, e.g. a tab 323, along a part of the fitting outer circumference 306. The front housing part 104 is provided with at least a first slot, e.g. a slot 315, along a part of a fitting outer circumference 376. The fitting outer circumference 306 is fitted with the fitting outer circumference 376 to form a part of upper housing 102 (at least a part of the housing), where at least the first tab is inserted into the first slot. At least the first tab and the first slot are constituted, such that movement thereof along the fitting outer circumferences 306, 376 is limited between the front and rear housings 104, 106.

    PIPELINED DUAL PORT INTEGRATED CIRCUIT MEMORY

    公开(公告)号:JP2000030460A

    公开(公告)日:2000-01-28

    申请号:JP17069699

    申请日:1999-06-17

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To obtain a dual port RAM which is inexpensive and whose speed is high and whose capacity is large by providing an arbitration circuit judging which of first and second addresses is given to plural memories during the access to an integrated circuit memory to utilize single port RAMs. SOLUTION: A memory 20 includes a single port SRAM array 21, an arbitration circuit 24, bonding pads 26, 28, an input part 30 and an output part 50. At the time of an operation, the memory 20 functions as the static random access memory(SRAM) of a full dual port. The memory 20 generates an access request to the array 21 responding to an external access request. The arbitration circuit 24 assures that the earlier access request between two access requests is given to the array 21 except a time when the two access requests are actually received simultaneously and the priority is given to an X port when the requests are received simultaneously.

    DATA PROCESSING SYSTEM HAVING BRANCH CONTROL AND METHOD THEREFOR

    公开(公告)号:JP2000029700A

    公开(公告)日:2000-01-28

    申请号:JP17069799

    申请日:1999-06-17

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To minimize a clock cycle number by composing the system of a stage where a program loop is defined and a stage where a loop value is determined according to a backward branch instruction. SOLUTION: A data processor 10 is equipped with a CPU 12, a memory 14, a bus interface module 16, and other modules 18 coupled with one another in two directions through a bus 20. The memory 14 is coupled optionally to the outside of the data processor 10 through one or more integrated circuit circuit terminal 24. The CPU12 is coupled optionally to the outside of the data processor 10 through one or more integrated circuit circuit terminal 22. The data processor 10 executes instructions collected in order from the memory 14 until it encounters a variation instruction for a flow such as a branch instruction. In this case, the backward branch instruction executes branching to a target address in the memory 14, defines a program loop, and sets a loop value according to the backward branch instruction.

    TRANSPARENT COMPOUND AND ITS USE
    145.
    发明专利

    公开(公告)号:JP2000026744A

    公开(公告)日:2000-01-25

    申请号:JP12546999

    申请日:1999-05-06

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To obtain a molding compound having compatibility with both existing assembling treatment requirements and the optical requirements for optoelectronic devices. SOLUTION: Using a molding compound made from a polymeric resin and an isorefractive transparent filler, an optoelectronic part 10 is formed. Furthermore, a lens 13 on a display 10, the outside housing of a waveguide, or a dome reflecting light from a light-emitting device against a photodetector, can be formed using such a molding compound.

    ANTENNA COUPLING SYSTEM
    146.
    发明专利

    公开(公告)号:JPH11355024A

    公开(公告)日:1999-12-24

    申请号:JP13684599

    申请日:1999-05-18

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a system for keeping an antenna at a position vertical to the ground at the time of transmission or reception of a satellite subscriber unit by providing a standing wall which is coupled to a base, has inner and outer surfaces and partitions plural key receptacles and plural stoppers on the outer surface. SOLUTION: An antenna stem 108 is injection molded using polycarbonate and this antenna stem is provided with a base 202, leg part 204 coupled to the base 202, a first standing wall 206 coupled to an upper side 208 of the base 202 and a second standing wall coupled to the bottom side of the base 202. An opening 210 for housing an antenna container is extended through the first and second standing walls. The first standing wall 206 is provided with plural, preferably, four key receptacles 216, 218, 220 and 222 installed at equal intervals along an outer surface 214 of the standing wall 206. This outer surface 214 of the first standing wall 206 further partitions plural, preferably, three stoppers 224 or the like.

    MANUFACTURE OF INTEGRATED CIRCUIT
    147.
    发明专利

    公开(公告)号:JPH11354644A

    公开(公告)日:1999-12-24

    申请号:JP12811299

    申请日:1999-05-10

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To form a highly reliable phase window and a connection pad in an integrated circuit, by removing a part of a reflection suppression film prior to wire bonding, and leaving a part of a dielectric layer on a phase in an etching process used for removing a part of the reflection suppress film. SOLUTION: The exposed part 42 of a reflection suppression film 28 and the exposed part 40 of a dielectric layer 20 are etched prior to wire bonding. A part 44 of a conduction layer 26 is exposed and a phase window 45 on a phase 16 is formed. Thus, a wire is highly reliably connected to a bonding pad 30. In an etching process, a part 46 of the dielectric layer 20 on the phase 16 is left. Namely, the exposed part 42 and the exposed part 40 are simultaneously etched at same speed in the etching process. Thus, the phase is highly reliably formed. Consequently, the phase 16 is not exposed to an outer environment and the invasion of the phase 16 is suppressed.

    DATA PROCESSING SYSTEM HAVING OVERLEAD PAGED MEMORY CONTROL REGISTER

    公开(公告)号:JPH11338770A

    公开(公告)日:1999-12-10

    申请号:JP499299

    申请日:1999-01-12

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a data processing system capable of reducing the overhead of programming. SOLUTION: This data processing system has a CPU for performing access through a memory managing interface to various memories including a non- volatile memory. The memory managing interface supports the paging of a module in the non-volatile memory into a paged memory area specified in a memory map. Memory control registers 80-87 for controlling the programming and erasure of the non-volatile memory module are simultaneously mapped onto a memory map in the specified memory register area. In this case, pages 90-97 of the non-volatile memory and memory control registers 80-87 related to them are selected based on a single page selection register and mapped into the specified area inside the memory map.

    METHOD FOR DESIGNING INTEGRATED CIRCUIT

    公开(公告)号:JPH11330259A

    公开(公告)日:1999-11-30

    申请号:JP5497099

    申请日:1999-03-03

    Applicant: MOTOROLA INC

    Inventor: SLAMAN N SHAMON

    Abstract: PROBLEM TO BE SOLVED: To provide a method for designing an integrated circuit, using an idle mode vector. SOLUTION: This method comprises providing of a general list of transistors 27, 28, 29, 31, 32, 33, 34, and 36 of an integrated circuit 20. The transistors of the integrated circuit 20 have initial threshold voltage. The integrated circuit 20 is put in idle operation mode, by applying idle mode vector to inputs 21, 22, 23, and 24 of the integrated circuit 20. The threshold voltages of the transistors 27, 28, 29, 31, 32, 33, 34, and 36 of the integrated circuit 20, which being in 'off' operation mode, block current path to a ground electric potential are set to a threshold voltage higher than the initial threshold voltage. The threshold voltages of remaining transistors 27, 28, 29, 31, 32, 33, 34, and 36 of the integrated circuit 20 are set to a threshold voltage smaller than the initial threshold voltage.

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