公开(公告)号：KR100392254B1

公开(公告)日：2003-07-23

申请号：KR1020000073339

申请日：2000-12-05

Applicant: 한국전자통신연구원

Inventor： 김상기 ,  구진근 ,  김종대 ,  조경익

IPC: H01L27/02

Abstract: PURPOSE: A thin film inductor is provided to make an inductor and a semiconductor device combine into one chip, by including a trench in which an oxide layer formed in a depth direction of a substrate and a material for shielding electromagnetic wave are filled so that an influence of electromagnetic wave caused by the inductor formed on the same substrate is completely shielded. CONSTITUTION: The thin film inductor is formed on the semiconductor substrate(200), including the first coil(209-1), a magnetic thin film(210) and the second coil(209-2). A trench is formed in the depth direction of the semiconductor substrate so that the electromagnetic wave generated from the thin film inductor does not outflow through the semiconductor substrate.

Abstract translation: 目的：提供薄膜电感器以通过包括其中在基板的深度方向上形成的氧化物层和用于屏蔽电磁波的材料被填充的沟槽来将电感器和半导体器件合并为一个芯片， 由在同一基板上形成的电感引起的电磁波的影响被完全屏蔽。 构成：薄膜电感器形成在包括第一线圈（209-1），磁性薄膜（210）和第二线圈（209-2）的半导体衬底（200）上。 在半导体衬底的深度方向上形成沟槽，使得从薄膜电感器产生的电磁波不会流出半导体衬底。

公开(公告)号：KR1020030052491A

公开(公告)日：2003-06-27

申请号：KR1020010082476

申请日：2001-12-21

Applicant: 한국전자통신연구원

Inventor： 구진근 ,  김상기 ,  박일용 ,  김종대

IPC: H01L27/02

Abstract: PURPOSE: An one chip type thin film inductor and a method for manufacturing the same are provided to be capable of reducing the size and weight of a chip module package by forming an IC(Integrated Circuit) and the thin film inductor on the same semiconductor substrate. CONSTITUTION: The first and second well region(221,241) are formed in a semiconductor substrate(200). The first and second MOS(Metal Oxide Semiconductor) transistor(pMOS,nMOS) are formed on the first and second well region, respectively. A plurality of metal layer patterns(202,204) are electrically connected between the first and second MOS transistor and impurity regions(222,242). A protecting isolation layer(205) is located on the resultant structure for separating the metal layer patterns. A lower core layer pattern(262) is formed on the predetermined portion of the protecting isolation layer. The first polyimide layer(261), a metal coil layer(264), the second polyimide layer(263), an upper core layer pattern(269), and the third polyimide layer(267) are sequentially formed on the resultant structure.

Abstract translation: 目的：提供一种单片式薄膜电感器及其制造方法，能够通过在同一半导体衬底上形成IC（集成电路）和薄膜电感器来减小芯片组件封装的尺寸和重量 。 构成：第一和第二阱区（221,241）形成在半导体衬底（200）中。 第一和第二MOS（金属氧化物半导体）晶体管（pMOS，nMOS）分别形成在第一和第二阱区上。 多个金属层图案（202,204）电连接在第一和第二MOS晶体管与杂质区（222,242）之间。 保护隔离层（205）位于所得结构上，用于分离金属层图案。 在保护隔离层的预定部分上形成下芯层图案（262）。 在所得结构上依次形成第一聚酰亚胺层（261），金属线圈层（264），第二聚酰亚胺层（263），上芯层图案（269）和第三聚酰亚胺层（267）。

公开(公告)号：KR100345400B1

公开(公告)日：2002-07-26

申请号：KR1019990043377

申请日：1999-10-08

Applicant: 한국전자통신연구원

Inventor： 김상기 ,  김종대 ,  남기수 ,  구진근

IPC: H01L21/76

Abstract: 본발명은반도체소자의공정기술에있어서소자의격리, 커패시터및 트렌치게이트제조시에이용되는트렌치(trench) 형성방법에관한것으로, 트렌치코너에서성장되는산화막두께를기존의방법으로성장시킨두께보다두껍게성장시켜전체적으로트렌치내면에균일한산화막을성장시키거나코너부분의열산화막을더 두껍게성장시키는트렌치형성방법에관한것이다. 본발명은 (100) 실리콘기판위에트렌치를형성하고난 후트렌치코너상부코너부분의산화막혹은질화막을 300Å ~ 3000Å정도습식식각한후 1000℃~1200℃의 고온에서수소를주입하여열처리함으로써트렌치내벽및 코너부분의결정면을재배열시켜각각의재배열된면에각각다른산화막성장속도를갖게하는것이다. 즉트렌치코너부분은산화막성장속도가가장빠른 (111) 결정면이생성되어단위시간당다른면보다두꺼운산화막이성장된다. 따라서, 열산화막성장시간을조절함으로써트렌치내부에균일한산화막혹은트렌치코너에더 두꺼운산화막을성장시킬수 있게된다. 그결과전기적특성특히소자의신뢰성은크게향상시킬수 있다

公开(公告)号：KR1020020054110A

公开(公告)日：2002-07-06

申请号：KR1020000082805

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  김상기 ,  구진근 ,  노태문 ,  이대우 ,  조경익

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

Abstract: PURPOSE: A trench gate power device using hydrogen annealing and self-aligned technology is provided to remarkably reduce fabricating cost, by using three masks of fabricating a trench gate power metal oxide semiconductor field effect transistor(MOSFET), and to improve on-resistance by forming a source while a sidewall oxide layer and the self-aligned technology are used. CONSTITUTION: A hydrogen annealing process is performed regarding a trench to round the corner portion of the trench so that a uniform oxide layer is grown on the trench to improve an electrical characteristic. The annealing process is performed by using a pull-back region which is generated by removing a trench sidewall oxide layer.

Abstract translation: 目的：通过使用制造沟槽栅极功率金属氧化物半导体场效应晶体管（MOSFET）的三个掩模，提供使用氢退火和自对准技术的沟槽栅极功率器件，以显着降低制造成本，并通过 在使用侧壁氧化物层和自对准技术的同时形成源极。 构成：对沟槽进行氢退火处理以使沟槽的拐角部分圆周化，使得在沟槽上生长均匀的氧化物层以改善电特性。 通过使用通过去除沟槽侧壁氧化物层产生的拉回区域来执行退火处理。

公开(公告)号：KR1020020049162A

公开(公告)日：2002-06-26

申请号：KR1020000078264

申请日：2000-12-19

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  김종대 ,  김상기 ,  이대우 ,  구진근 ,  조경익

IPC: H01L27/04

Abstract: PURPOSE: A method for fabricating a power integrated circuit is provided to remarkably reduce a high temperature annealing process for fabricating the power integrated circuit, by mixing a non-reduced surface field(RESURF) n-lateral double diffused metal oxide semiconductor(LDMOS) transistor and a RESURF p-LDMOS transistor. CONSTITUTION: The power integrated circuit includes the RESURF LDMOS transistor using a silicon-on-insulator, the non-RESURF LDMOS transistor of an opposite type to the RESURF LDMOS transistor and a logic complementary metal oxide semiconductor(CMOS). The regions where the logic CMOS as a low voltage device and an LDMOS transistor as a high power device are fabricated are doped with the same impurity type in a silicon substrate.

Abstract translation: 目的：提供一种制造功率集成电路的方法，通过混合非还原表面场（RESURF）n侧双扩散金属氧化物半导体（LDMOS）晶体管，显着降低制造功率集成电路的高温退火工艺 和RESURF p-LDMOS晶体管。 构成：功率集成电路包括使用绝缘体上硅的RESURF LDMOS晶体管，与RESURF LDMOS晶体管相反类型的非RESURF LDMOS晶体管和逻辑互补金属氧化物半导体（CMOS）。 制造作为低电压器件的逻辑CMOS和作为高功率器件的LDMOS晶体管的区域在硅衬底中掺杂相同的杂质类型。

公开(公告)号：KR1020020043996A

公开(公告)日：2002-06-14

申请号：KR1020000073473

申请日：2000-12-05

Applicant: 한국전자통신연구원

Inventor： 구진근 ,  노태문 ,  이대우 ,  김상기 ,  김종대

IPC: H01L21/336

Abstract: PURPOSE: A method for fabricating a high-current power integrated circuit is provided to decrease the size of a high-current integrated circuit(IC) chip, by integrating a high-current trench gate DMOS power device and high-voltage lateral double diffused MOS(LDMOS) and complementary MOS(CMOS) devices in an n-type epitaxial layer on a p-type silicon substrate. CONSTITUTION: A thick thermal oxide layer is grown on the p-type silicon substrate(1) and a photolithography process is performed regarding the thermal oxide layer to define an n-type buried layer(2). The density of the n-type buried layer is controlled according to a breakdown voltage. Phosphorous ions are implanted into the n-type buried layer and are diffused in an oxidation atmosphere so that a phosphorous-doped n-type epitaxial layer is grown. An n-well and a p-well are formed, wherein a high temperature heat treatment process is performed to make the junction of the n-type buried layer out-diffused to a lower portion of a gate electrode. A trench device is isolated. A p-body junction is formed as a channel region of a trench gate DMOS. A field oxide layer region is defined and a field threshold voltage is controlled. An oxide layer is grown. A gate oxide layer of the high-voltage LDMOS and CMOS devices is grown, and a threshold voltage is controlled to form the gate electrode. An LDD junction is formed and a sidewall oxide layer(17) is formed. The source and drain of the CMOS and LDMOS trench gate DMOS devices are joined and a metal interconnection is formed.

Abstract translation: 目的：提供一种大电流功率集成电路的制造方法，通过集成高电流沟槽栅极DMOS功率器件和高电压侧向双扩散MOS（MOS）功率来减小大电流集成电路（IC）芯片的尺寸 （LDMOS）和互补MOS（CMOS）器件在p型硅衬底上的n型外延层中。 构成：在p型硅衬底（1）上生长厚的氧化物层，并且对热氧化层进行光刻工艺以限定n型掩埋层（2）。 n型掩埋层的密度根据击穿电压进行控制。 将磷离子注入到n型掩埋层中并在氧化气氛中扩散，从而生长磷掺杂的n型外延层。 形成n阱和p阱，其中进行高温热处理工艺以使n型掩埋层的结外扩散到栅电极的下部。 隔离沟槽装置。 p体结形成为沟槽栅DMOS的沟道区。 定义场氧化物层区域并控制场阈值电压。 生长氧化物层。 生长高压LDMOS和CMOS器件的栅极氧化层，并且控制阈值电压以形成栅电极。 形成LDD结，形成侧壁氧化物层（17）。 CMOS和LDMOS沟槽栅极DMOS器件的源极和漏极被连接并形成金属互连。

公开(公告)号：KR100289057B1

公开(公告)日：2001-10-24

申请号：KR1019970070310

申请日：1997-12-19

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  이상용 ,  김상기 ,  구진근 ,  남기수

IPC: H01L29/78

Abstract: PURPOSE: A structure of a high voltage double diffused power device is provided to reduce efficiently a breakdown effect generating between a channel surface and a drift region by forming a ring for limiting a buried electric field on the drift region. CONSTITUTION: A buried oxide layer(102) and an epitaxial layer(103) are formed on substrate(101) to enhance a breakdown voltage and an on-resistance value of a high voltage double diffused power device. After forming a well region(104) and a drift region(105) on the epitaxial layer, a well contact point(106) and a source(107) are formed on the well region(104) and a drain(108) is formed on the drift region(105). A buried electric field limiting ring is formed by implanting a different impurity ion with an ion of the drift region using a high energy ion injection process to increase a breakdown voltage, thereby reducing a surface electric field effect in the drift region. A gate oxide layer(109) is formed on the well region and the drift region. A gate metal(111), a source metal(112) and a drain metal(110) are formed.

公开(公告)号：KR1020010048716A

公开(公告)日：2001-06-15

申请号：KR1019990053515

申请日：1999-11-29

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  김상기 ,  구진근 ,  남기수 ,  이대우 ,  노태문

IPC: H01L27/085

CPC classification number: H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

Abstract: PURPOSE: A method for manufacturing a trench gate power device using a self-aligned technology is provided to form a trench double diffused metal-oxide-semiconductor(TDMOS) power device by using only three masks wherein a trench sidewall layer and a self-aligned technique are utilized. CONSTITUTION: After an oxide layer and a nitride layer are sequentially grown on a silicon substrate, impurity ions are implanted by using the first mask to form a channel layer of a device. After a sidewall oxide layer and a trench are sequentially formed on the resultant structure, the sidewall oxide layer is eliminated to implant impurity ions into the bottom surface of the trench and into the region where the sidewall layer is eliminated. A gate oxide layer is grown on the surface of the trench. Polycrystalline silicon is filled inside the trench by using the second mask to form a gate electrode. An oxide layer is deposited on the trench, and an etch-back process is performed until the nitride layer is exposed. The nitride layer is removed. Impurity ions are implanted to form a body contact by using a self-aligned technology. An electrode for forming a terminal is formed on the resultant structure by using the third mask.

Abstract translation: 目的：提供一种使用自对准技术制造沟槽栅极功率器件的方法，以通过仅使用三个掩模形成沟槽双扩散金属氧化物半导体（TDMOS）功率器件，其中沟槽侧壁层和自对准 技术被利用。 构成：在硅衬底上依次生长氧化物层和氮化物层之后，通过使用第一掩模注入杂质离子以形成器件的沟道层。 在所得结构上顺序地形成侧壁氧化物层和沟槽之后，消除侧壁氧化物层，以将杂质离子注入到沟槽的底表面中，并进入去除侧壁层的区域。 栅极氧化层生长在沟槽表面上。 通过使用第二掩模将多晶硅填充在沟槽内部以形成栅电极。 在沟槽上沉积氧化物层，并且进行回蚀处理直至暴露氮化物层。 去除氮化物层。 通过使用自对准技术植入杂质离子以形成身体接触。 通过使用第三掩模，在所得结构上形成用于形成端子的电极。

公开(公告)号：KR1020010028167A

公开(公告)日：2001-04-06

申请号：KR1019990040257

申请日：1999-09-18

Applicant: 한국전자통신연구원

Inventor： 남기수 ,  김상기 ,  구진근 ,  조경익

IPC: H01L27/085

Abstract: PURPOSE: A method for manufacturing a trench gate power device is provided to reduce the number of etching masks, by forming a source region after an N- well or P- well is formed by using a trench gate mask and a sidewall layer is formed to manufacture a trench gate. CONSTITUTION: After N- epi layer(2) is grown and an oxide layer is formed on an N+ silicon substrate, a portion for a trench gate is defined and etched to form a P- well(5). A layer for forming a sidewall layer and the trench gate is formed. After a portion of the sidewall layer is defined, the layer for the sidewall layer is etched to form the sidewall layer. The N- epi layer is etched by a depth deeper than that of the P- well to form the trench structure. After a gate oxide layer(9) is grown, a polycrystalline silicon thin film doped with impurities is deposited to fill a trench. The polycrystalline silicon thin film is anisotropically etched to form a polycrystalline gate structure(10). After the sidewall layer is removed, N+ impurity ions are implanted into the region where the sidewall layer is eliminated, to form a source region(11). The oxide layers(3,4) are etched and a field oxide layer(12) are grown. A portion where a source electrode(13) contacts a gate electrode is formed. After a metal layer is deposited to form the source electrode and the gate electrode, a drain electrode(14) is formed on a back side of the substrate.

Abstract translation: 目的：提供一种用于制造沟槽栅极功率器件的方法，以通过在通过使用沟槽栅极掩模形成N阱或P-阱之后形成源极区域来减少蚀刻掩模的数量，并且将侧壁层形成为 制造沟槽门。 构成：在N外延层（2）生长并且在N +硅衬底上形成氧化物层之后，限定并蚀刻用于沟槽栅极的部分以形成P阱（5）。 形成用于形成侧壁层和沟槽栅极的层。 在限定侧壁层的一部分之后，蚀刻用于侧壁层的层以形成侧壁层。 通过深度比P-阱的深度蚀刻N外延层以形成沟槽结构。 在栅极氧化物层（9）生长之后，沉积掺杂有杂质的多晶硅薄膜以填充沟槽。 多晶硅薄膜被各向异性蚀刻以形成多晶栅极结构（10）。 在去除侧壁层之后，将N +杂质离子注入到去除侧壁层的区域中以形成源极区域（11）。 蚀刻氧化物层（3,4）并生长场氧化物层（12）。 形成源电极（13）与栅电极接触的部分。 在沉积金属层以形成源电极和栅电极之后，在基板的背面形成漏电极（14）。

公开(公告)号：KR100275484B1

公开(公告)日：2001-01-15

申请号：KR1019980044520

申请日：1998-10-23

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  김상기 ,  구진근 ,  남기수 ,  김대용

IPC: H01L29/78

Abstract: 본 발명은 비교적 용이한 공정으로 트렌치의 가장자리를 완만하게하며 트렌치 가장자리에 상대적으로 두껍게 산화막을 형성할 수 있어 트렌치 게이트 전극의 가장자리에 전기장이 집중되는 것을 억제하고 전력소자의 항복전압을 증가시키고 누설전류를 감소시킬 수 있는 트렌치형 게이트 전극을 갖는 전력소자 제조 방법에 관한 것으로, 본 발명은 1차 건식식각으로 얕은 트렌치를 형성시키고 습식식각을 실시하여 얕은 트렌치 형성시 사용된 식각마스크의 측벽을 언더컷(under cut) 형태로 완만하게 한 후, 얕은 트렌치의 저면을 2차 건식식각하여 주 트렌치(main trench)를 형성함과 동시에 주 트렌치(main trench)에 인접한 부분에 기생 트렌치(parasitic trench)가 형성되도록 하여 이후의 산화막 형성 공정에서 기생 트렌치 부분에 상대적으로 두꺼운 산화막이 형� �되도록 함으로써 트렌치 가장자리에 인가되는 전기장의 크기를 줄이는데 그 특징이 있다.