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公开(公告)号：SG11201701614WA
公开(公告)日：2017-03-30
申请号：SG11201701614W
申请日：2015-09-14
Applicant: IBM
Inventor： FARRELL MARK , HELLER LISA , KUBALA JEFFREY PAUL , SCHMIDT DONALD WILLIAM , GREINER DAN , SLEGEL TIMOTHY , BUSABA FADI YUSUF , OSISEK DAMIAN , BRADBURY JONATHAN DAVID , LEHNERT FRANK , NERZ BERND , JACOBI CHRISTIAN
Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.
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公开(公告)号：DE112015001477T5
公开(公告)日：2017-02-16
申请号：DE112015001477
申请日：2015-03-17
Applicant: IBM
Inventor： BRADBURY JONATHAN DAVID , SCHMIDT DONALD WILLIAM , ROSA DANIEL VINCENT , BARTIK JANE , KING GARY MALCOM
Abstract: Ausführungsformen beziehen sich auf ein Verfolgen einer Auslastung in einem Multithreading(MT)-Computersystem. Gemäß einem Aspekt beinhaltet ein Computersystem eine Konfiguration mit einem Kern, der so konfiguriert ist, dass er in einem MT-Modus betrieben wird, der mehrere Threads in gemeinsam genutzten Ressourcen des Kerns unterstützt. Der Kern ist so konfiguriert, dass er ein Verfahren durchführt, das ein Zurücksetzen einer Mehrzahl von Auslastungszählern beinhaltet. Die Auslastungszähler beinhalten eine Mehrzahl von Zählersätzen. Während jedes Taktzyklus auf dem Kern wird aus der Mehrzahl von Zählersätzen ein Satz von Zählern ausgewählt. Das Auswählen beruht auf einer Anzahl von momentan aktiven Threads auf dem Kern. Zusätzlich wird auf Grundlage eines Zusammentreffens von einem oder mehreren Ausführungsereignissen in den mehreren Threads des Kerns während jedes Taktzyklus ein Zähler in dem ausgewählten Satz von Zählern erhöht. Die Werte der Auslastungszähler werden einem Softwareprogramm bereitgestellt.
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公开(公告)号：AU2013375139B2
公开(公告)日：2017-02-02
申请号：AU2013375139
申请日：2013-12-04
Applicant: IBM
Inventor： BRADBURY JONATHAN DAVID , SCHWARZ ERIC MARK
IPC: G06F9/30
Abstract: A Vector Checksum instruction. Elements from a second operand are added together one- by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.
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公开(公告)号：AU2015238706A1
公开(公告)日：2016-08-04
申请号：AU2015238706
申请日：2015-03-06
Applicant: IBM
Inventor： HELLER LISA CRANTON , KUBALA JEFFREY PAUL , BUSABA FADI YUSUF , BRADBURY JONATHAN DAVID , FARRELL MARK , OSISEK DAMIAN LEO , GREINER DAN , SLEGEL TIMOTHY , SCHMIDT DONALD WILLIAM , GAINEY CHARLES , JACOBI CHRISTIAN
Abstract: Embodiments relate to multithreading in a computer. An aspect is a computer including a configuration having a core which includes physical threads and is operable in single thread (ST) and multithreading (MT) modes. The computer also includes a host program configured to execute in the ST mode on the core to issue a start-virtual-execution (start-VE) instruction to dispatch a guest entity which includes a guest virtual machine (VM). The start-VE instruction is executed by the core and includes obtaining a state description, having a guest state, from a location specified by the start-VE instruction. The execution includes determining, based on the guest state, whether the guest entity includes a single guest thread or multiple guest threads, and starting the guest threads in the MT mode or ST mode based on the guest state and a determination of whether the guest entity includes a single guest thread or multiple guest threads.
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Patent Agency Ranking
公开(公告)号：MX340052B
公开(公告)日：2016-06-22
申请号：MX2015009458
申请日：2013-12-06
Applicant: IBM
Inventor： SLEGEL TIMOTHY , SCHWARZ ERIC MARK , BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL
IPC: G06F17/16
Abstract: Se facilita el manejo de la excepción del vector. Se ejecuta una instrucción vectorial que opera en uno o más elementos de un registro del vector. Cuando una excepción se encuentra durante la ejecución de la instrucción, se proporciona un código de excepción del vector, que indica una posición dentro del registro del vector que causó la excepción. El código de excepción del vector también incluye una razón para la excepción.
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公开(公告)号：CA2961708A1
公开(公告)日：2016-06-09
申请号：CA2961708
申请日：2015-10-30
Applicant: IBM
Inventor： BRADBURY JONATHAN DAVID , JACOBI CHRISTIAN , SLEGEL TIMOTHY , GSCHWIND MICHAEL KARL
Abstract: A method for accessing data in a memory coupled to a processor comprising: receiving a memory reference instruction for accessing data of a first size at an address in the memory; determining an alignment size of the address in the memory; and accessing the data of the first size in one or more groups of data by accessing each group of data block concurrently. The groups of data have sizes that are multiples of the alignment size.
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公开(公告)号：AU2013233993B2
公开(公告)日：2016-05-19
申请号：AU2013233993
申请日：2013-03-07
Applicant: IBM
Inventor： BRADBURY JONATHAN DAVID , SLEGEL TIMOTHY , SCHWARZ ERIC MARK , GSCHWIND MICHAEL KARL
Abstract: Processing of character data is facilitated. A Find Element Equal instruction is provided that compares data of multiple vectors for equality and provides an indication of equality, if equality exists. An index associated with the equal element is stored in a target vector register. Further, the same instruction, the Find Element Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.
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公开(公告)号：GB2525357A
公开(公告)日：2015-10-21
申请号：GB201514708
申请日：2013-11-21
Applicant: IBM
IPC: G06F9/30
Abstract: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction.
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公开(公告)号：CA2940982A1
公开(公告)日：2015-10-01
申请号：CA2940982
申请日：2015-03-16
Applicant: IBM
Inventor： HELLER LISA CRANTON , BRADBURY JONATHAN DAVID , KUBALA JEFFREY PAUL , FARRELL MARK , OSISEK DAMIAN LEO , GREINER DAN , SLEGEL TIMOTHY , BUSABA FADI YUSUF , SCHMIDT DONALD WILLIAM , GAINEY CHARLES JR
Abstract: A computer system includes a virtual machine (VM) configuration with one or more cores. Each core is enabled to operate in a single thread (ST) mode or a multithreading (MT) mode. The ST mode consists of a single thread and the MT mode consists of a plurality of threads on shared resources of a respective core. The computer system includes a core-oriented system control area (COSCA) having a common area representing all of the cores of the VM configuration and separate core description areas for each of the cores in the VM configuration. Each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread.
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