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    Piezoresistive sensing structure
    144.
    发明申请
    Piezoresistive sensing structure 审中-公开
    压阻感测结构

    公开(公告)号：US20080179698A1

    公开(公告)日：2008-07-31

    申请号：US12079726

    申请日：2008-03-28

    Applicant: David B. Rich ,  Steven M. Crist

    Inventor： David B. Rich ,  Steven M. Crist

    IPC: H01L29/08

    CPC classification number: B81C1/00142 ,  B81B2201/0235 ,  B81B2201/032 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C2201/016 ,  G01P15/0802 ,  G01P15/123 ,  G01P2015/0828

    Abstract: A piezoresistive sensing structure includes an assembly formed of a semiconductor material and including a cavity and a plurality of piezoresistive elements implanted into the assembly. The assembly includes a central mass coupled to a peripheral frame with a plurality of beams. Each beam is about 15 microns in width and includes one of the piezoresistive elements. The assembly may also include a first wafer having the cavity formed into a first side, and a second wafer with a plurality of beams formed in a first side. The second side of the second wafer is bonded to the first side of the first wafer.

    Abstract translation: 压阻感测结构包括由半导体材料形成并包括腔体和多个压电元件的组件，所述压电元件植入组件中。 组件包括耦合到具有多个梁的外围框架的中心质量。 每个光束的宽度约为15微米，并且包括压阻元件之一。 组件还可以包括具有形成为第一侧的空腔的第一晶片和在第一侧中形成有多个梁的第二晶片。 第二晶片的第二面被结合到第一晶片的第一侧。

    Method of micromachining a multi-part cavity
    147.
    发明授权
    Method of micromachining a multi-part cavity 失效
    微加工多部分腔体的方法

    公开(公告)号：US06827869B2

    公开(公告)日：2004-12-07

    申请号：US10194167

    申请日：2002-07-11

    Applicant: Dragan Podlesnik ,  Thorsten Lill ,  Jeff Chinn ,  Shaoher X. Pan ,  Anisul Khan ,  Maocheng Li ,  Yiqiong Wang

    Inventor： Dragan Podlesnik ,  Thorsten Lill ,  Jeff Chinn ,  Shaoher X. Pan ,  Anisul Khan ,  Maocheng Li ,  Yiqiong Wang

    IPC: H01L21302

    CPC classification number: H01L27/1087 ,  B81B2201/052 ,  B81B2203/0315 ,  B81B2203/033 ,  B81C1/00119 ,  B81C2201/016 ,  H01L21/3065 ,  H01L21/3086

    Abstract: The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes. The method is also useful whenever it is necessary to maintain tight control over the dimensions of the shaped opening.

    Abstract translation: 本公开涉及我们发现用于蚀刻衬底中的多部分空腔的特别有效的方法。 该方法提供了首先蚀刻成形开口，在成形开口的内表面的至少一部分上沉积保护层，然后直接在成形开口下面蚀刻成形腔，并与成形开口连续连通。 保护层在蚀刻成形腔体期间保护成形开口的蚀刻轮廓，从而如果需要，成形开口和成形腔体可以被蚀刻以具有不同的形状。 在本发明方法的特定实施例中，横向蚀刻阻挡层和/或注入的蚀刻停止点也用于引导蚀刻工艺。 本发明的方法可以应用于需要或期望提供具有不同形状的成形开口和下面的成形腔的任何应用。 只要需要对成形开口的尺寸进行严格控制，该方法也是有用的。

    Anisotropic dry etching technique for deep bulk silicon etching
    148.
    发明授权
    Anisotropic dry etching technique for deep bulk silicon etching 失效
    用于深体硅蚀刻的各向异性干蚀刻技术

    公开(公告)号：US06790779B2

    公开(公告)日：2004-09-14

    申请号：US10202331

    申请日：2002-07-24

    Applicant: James H. Schermerhorn ,  Matthew C. Nielsen ,  Richard J. Saia ,  Jeffrey B. Fortin

    Inventor： James H. Schermerhorn ,  Matthew C. Nielsen ,  Richard J. Saia ,  Jeffrey B. Fortin

    IPC: H01L21302

    CPC classification number: B81C1/00619 ,  B81B2203/033 ,  B81C1/00412 ,  B81C2201/0132 ,  B81C2201/016 ,  H01L21/0332 ,  H01L21/3065 ,  H01L21/3081 ,  Y10S438/964

    Abstract: A method for creating deep features in a Si-containing substrate for use in fabricating MEMS type devices is provided. The method includes first forming a thin Ni hardmask on a surface of a Si-containing substrate. The Ni hardmask is patterned using conventional photolithography and wet etching so as to expose at least one portion of the underlying Si-containing substrate. The at least one exposed portion of the Si-containing substrate, not containing the patterned hardmask, is then etched in a plasma that includes free radicals generated from a gaseous mixture of chlorine (Cl2), sulfur hexafluoride (SF6) and oxygen (O2). The interaction of the gas species in the plasma yields a rapid silicon etch rate that is highly selective to the Ni hardmask. The etch rate ratio of Si to Ni using the inventive method is greater than 250:1.

    Abstract translation: 提供了一种用于制造用于制造MEMS型器件的含Si衬底中的深度特征的方法。 该方法包括首先在含Si衬底的表面上形成薄的Ni硬掩模。 使用常规的光刻和湿法刻蚀图案化Ni硬掩模，以暴露下面的含Si衬底的至少一部分。 然后，在包含由氯（Cl 2），六氟化硫（SF 6）和氧气（O 2）的气体混合物产生的自由基的等离子体中蚀刻含有图案化硬掩模的含Si衬底的至少一个暴露部分， 。 等离子体中的气体物质的相互作用产生了对Ni硬掩模高度选择性的快速硅蚀刻速率。 使用本发明方法的Si与Ni的蚀刻速率比大于250:1。

    Integrated driver process flow
    149.
    发明授权
    Integrated driver process flow 有权

    公开(公告)号：US06767751B2

    公开(公告)日：2004-07-27

    申请号：US10161191

    申请日：2002-05-28

    Applicant: James A. Hunter

    Inventor： James A. Hunter

    IPC: H01L2100

    CPC classification number: G02B26/0808 ,  B81B2201/045 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/016 ,  B81C2203/0735 ,  B81C2203/0778 ,  H01L27/0611

    Abstract: An integrated device including one or more device drivers and a diffractive light modulator monolithically coupled to the one or more driver circuits. The one or more driver circuits are configured to process received control signals and to transmit the processed control signals to the diffractive light modulator. A method of fabricating the integrated device preferably comprises fabricating a front-end portion for each of a plurality of transistors, isolating the front-end portions of the plurality of transistors, fabricating a front-end portion of a diffractive light modulator, isolating the front end portion of the diffractive light modulator, fabricating interconnects for the plurality of transistors, applying an open array mask and wet etch to access the diffractive light modulator, and fabricating a back-end portion of the diffractive light modulator, thereby monolithically coupling the diffractive light modulator and the plurality of transistors.

    Composite dielectric with improved etch selectivity for high voltage MEMS structures
    150.
    发明授权
    Composite dielectric with improved etch selectivity for high voltage MEMS structures 有权
    具有改进的高电压MEMS结构的蚀刻选择性的复合电介质

    公开(公告)号：US06747338B1

    公开(公告)日：2004-06-08

    申请号：US10306639

    申请日：2002-11-27

    Applicant: Thomas K. Nunan ,  David E. Grosjean ,  Denis M. O'Kane ,  James S. Sellars

    Inventor： Thomas K. Nunan ,  David E. Grosjean ,  Denis M. O'Kane ,  James S. Sellars

    IPC: H01L2358

    CPC classification number: B81C1/00595 ,  B81C1/00698 ,  B81C2201/0109 ,  B81C2201/0142 ,  B81C2201/016 ,  B81C2201/019

    Abstract: A method of manufacturing MEMS structures and devices that allows the fabrication of dielectric structures with improved etch selectivity and good electrical leakage characteristics. The dielectric structure includes a composite stack of silicon nitride sub-layers with a silicon-rich nitride sub-layer and a stoichiometric silicon nitride sub-layer at opposite ends of the stack. Alternatively, the dielectric structure includes a single silicon nitride layer providing a graded change in silicon content through the dielectric layer, from silicon-rich nitride to stoichiometric silicon nitride.

    Abstract translation: 制造MEMS结构和器件的方法，其允许制造具有改进的蚀刻选择性和良好漏电特性的电介质结构。 电介质结构包括在堆叠的相对端处具有富硅氮化物子层和化学计量氮化硅子层的氮化硅子层的复合叠层。 或者，电介质结构包括单个氮化硅层，其通过介电层提供硅含量的梯度变化，从富含硅的氮化物到化学计量的氮化硅。

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