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    152.
    发明专利
    未知

    公开(公告)号：DE69412230D1

    公开(公告)日：1998-09-10

    申请号：DE69412230

    申请日：1994-02-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

    Abstract: A method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with columns of memory elements grouped together to form portions of a bidimensional array of memory elements, the column redundancy circuitry comprising at least one plurality of non-volatile memory registers (RR1-RR4) each one associated to a respective redundancy column of redundancy memory elements and each one programmable to store an address of a defective column and an identifying code (MCS7-MCS10) for identifying the portion of the bidimensional array to which the defective column belongs, provides for supplying each non-volatile memory register (RR1-RR4) with column address signals (CABUS) and with a first subset (R1-R4) of row address signals (RABUS), which when one of the non-volatile memory registers (RR1-RR4) is to be programmed carry the address of a defective column and said identifying code (MCS7-MCS10) respectively, and for activating one signal of a second subset (R5-R8) of the row address signals (RABUS), supplied to programming selection means (6), for selecting one respective non-volatile memory register (RR1-RR4) of said plurality to cause the data carried by the column address signals (CABUS) and by the first subset (R1-R4) of the row address signals to be programmed into said one respective non-volatile memory register (RR1-RR4).

    153.
    发明专利
    未知

    公开(公告)号：DE69224576D1

    公开(公告)日：1998-04-09

    申请号：DE69224576

    申请日：1992-08-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C17/18 ,  G11C8/10 ,  G11C17/12 ,  G11C8/00

    Abstract: A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection means driven through five buses for implementing a two-level decoding, thus driving a fractionary number of rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.

    154.
    发明专利
    未知

    公开(公告)号：DE69222712T2

    公开(公告)日：1998-02-12

    申请号：DE69222712

    申请日：1992-07-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

    Abstract: The discriminating sensitivity of a sense amplifier and the speed of the circuit are increased by exploiting the difference of potential which develops across the output nodes of the two control circuits, employed for enabling/disabling current paths of the input network of the differential amplifier, as a virtual additional signal for the sensing differential amplifier, by employing said output potentials of the two control circuits as virtual reference potentials for the pair of input transistors of the differential amplifier during a discriminating phase of the reading cycle. Two pass-transistors driven by a control signal provide to force to ground potential the output nodes of said control circuits, thus reestablishing a correct ground reference potential of the amplifier, during the final phase of amplification and storage of the extracted datum in an output latch, as well as during the successive standby period. Alternative embodiments also include various anti-overshoot circuits.

    155.
    发明专利
    未知

    公开(公告)号：DE69222712D1

    公开(公告)日：1997-11-20

    申请号：DE69222712

    申请日：1992-07-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

    Abstract: The discriminating sensitivity of a sense amplifier and the speed of the circuit are increased by exploiting the difference of potential which develops across the output nodes of the two control circuits, employed for enabling/disabling current paths of the input network of the differential amplifier, as a virtual additional signal for the sensing differential amplifier, by employing said output potentials of the two control circuits as virtual reference potentials for the pair of input transistors of the differential amplifier during a discriminating phase of the reading cycle. Two pass-transistors driven by a control signal provide to force to ground potential the output nodes of said control circuits, thus reestablishing a correct ground reference potential of the amplifier, during the final phase of amplification and storage of the extracted datum in an output latch, as well as during the successive standby period. Alternative embodiments also include various anti-overshoot circuits.

    158.
    发明专利
    未知

    公开(公告)号：ITVA910022D0

    公开(公告)日：1991-07-31

    申请号：ITVA910022

    申请日：1991-07-31

    Applicant: ST MICROELECTRONICS SRL ,  SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413

    Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by implifying the sensing process.

    160.
    发明专利
    未知

    公开(公告)号：DE60230129D1

    公开(公告)日：2009-01-15

    申请号：DE60230129

    申请日：2002-07-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C16/16 ,  G11C8/02 ,  G11C8/12 ,  G11C16/08

    Abstract: A line selector for a matrix of memory elements, for example a word line selector, comprises a plurality of line group selection circuits (1031-103p,107,399), each one allowing the selection (PSS1-PSSp) of a respective group of matrix lines (WL1-WLk,...,WLq-WLm) according to an address (RADD1); each matrix line group includes at least one matrix line. Flag means (303) are associated with each line group, that can be set (307,LD-ER) to declare a pending status of a prescribed operation, for example an erase operation, for the respective matrix line group. Means (301,319) are provided for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation (ER-P/VFY), in alternative to the respective line group selection circuit. The flag means enable, when set, the execution of the prescribed operation on the respective matrix line group.

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