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    2.
    发明专利
    未知

    公开(公告)号：ITVA910022D0

    公开(公告)日：1991-07-31

    申请号：ITVA910022

    申请日：1991-07-31

    Applicant: ST MICROELECTRONICS SRL ,  SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413

    Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by implifying the sensing process.

    REDUNDANT REGISTER PROGRAMMING METHOD AND COLUMN REDUNDANT INTEGRATED CIRCUIT
    7.
    发明专利
    REDUNDANT REGISTER PROGRAMMING METHOD AND COLUMN REDUNDANT INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH0822698A

    公开(公告)日：1996-01-23

    申请号：JP2664295

    申请日：1995-02-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

    Abstract: PURPOSE: To eliminate the need of generating an ON-CHIP exclusive signal to reduce the chip size by using the existing signal line in a memory to program a redundant register. CONSTITUTION: A two-dimensional array memory matrix provided with a 16-bit data bus is divided into a plurality of portions each of which is composed of a plurality of bit groups. Redundant registers RR1-4 composed of programmable non-volatile memory is capable of programming an address of the defective bit line received from a column address signal CABUS in its first block 1. Moreover, in the second block 2, an identification code MCS7-10 of the bit group to which a defective bit line belongs obtained from the first part R1-4 of the row address signal set RABUS. A programming selection means 6 selects the redundant register RR1-4 with the second part R5-8 of the row address signal set RABUS to store the address information of the defective bit line.

    TESTING METHOD FOR NONVOLATILE MEMORY
    8.
    发明专利
    TESTING METHOD FOR NONVOLATILE MEMORY 失效

    公开(公告)号：JPH07220500A

    公开(公告)日：1995-08-18

    申请号：JP1166395

    申请日：1995-01-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  MACCARRONE MARCO

    IPC: G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C29/56 ,  G11C16/06

    Abstract: PURPOSE: To execute a test faster by excluding an internal state machine and directly programming a cell matrix to testify that the program is correct. CONSTITUTION: A test circuit 10 receives a test mode active signal from an address bus 2 and a data bus 3, the positions of switches I1 to 3 are switched. The switch I1 is switched to a second circuit 8 (programming circuit) connecting a signal WEN to a memory matrix. The switch I2 is switched to a first circuit 6 (generator) connecting a signal CEN to a circuit 2 and a word line. The switch 3 directly input a signal OPE to the circuit 6 and an output buffer circuit 7. As the result of this, the internal state machine is excluded and addresses can freely be used. Then a new test method programming a desired cell through the use of a control signal with a new meaning and testifying that the program is correct is obtained.

    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT
    10.
    发明专利
    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT 失效

    公开(公告)号：JPH0855485A

    公开(公告)日：1996-02-27

    申请号：JP4796295

    申请日：1995-02-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To derive optimum performance from a memory by enabling the circuit with a switching edge, making the circuit programmable, and protecting the circuit against noise. CONSTITUTION: A delay unit 23 inputs a low-level signal, which goes up to a high level a delay time corresponding to the contents of memory elements 20 and 22 after a leading edge of a signal ATD is received, to a NOR gate 27. The gate 27 inputs a signal PC as a signal DET to an asymmetrical delay unit 24 through a NOR gate 28, and a low-level data simulation signal SP is outputted which goes up to the high level a delay time based upon the elements 20 and 21 after a leading edge of the signal DET is received. The signal SP is transferred to an output similar circuit 33 and at its completion time, a high level is outputted. Consequently, signals N and L are switched to the low level and the output STP of a continuance expanding circuit 51 goes down to a low level. Consequently, the data loading is completed. This loading lasts accurately in an output circuit 108 during data propagation.

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