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    Portable device for storing private information such as medical, financial or emergency information
    151.
    发明公开
    Portable device for storing private information such as medical, financial or emergency information 审中-公开
    便携式设备，用于存储个人数据，。 随着医疗，金融或紧急数据

    公开(公告)号：EP1914649A3

    公开(公告)日：2012-12-12

    申请号：EP07254156.8

    申请日：2007-10-19

    Applicant: STMicroelectronics, Inc

    Inventor： Le Neel, Olivier

    IPC: G06F19/00 ,  G06F21/00

    CPC classification number: G06F21/6218 ,  G06F19/00 ,  G16H10/65

    Abstract: A portable housing capable of being carried by a certain person includes a circuit. The circuit includes a memory for storing private data concerning that certain person, a circuit operable to effectuate storage of the private data in the memory in a secure manner, and a processing unit operable to control access to the memory for purposes of reading private data concerning the certain person from the memory and storing private data concerning the certain person to the memory. The conditions under which access to the memory for read and write operations with respect to the private data is permitted are governed by parameters that are specified by the certain person to whom the stored private data concerns. A biometric sensor may also be included to capture identification information useful in implementing the operations for controlling access to the memory.

    Abstract translation: 能够由某个人携带的便携式外壳，包括一电路。 该电路包括用于存储关于privateData做某些人，可操作的电路以实现私有数据存储在以安全的方式存储，以及处理单元，可操作用于控制对存储器的访问为读取专用数据关于目的的存储器 某些人从内存和存储privateData关于某些人的记忆。 在何种条件下访问内存进行读写操作相对于私人数据被允许通过参数管辖也被人取了一些存储的隐私数据的担忧中指定。 因此，一个生物特征传感器可以被包括以捕获在实施用于控制对存储器的访问的操作有用的识别信息。

    Micro-fludidic structure and method of making the same
    154.
    发明公开
    Micro-fludidic structure and method of making the same 审中-公开
    微流体结构及其制造方法

    公开(公告)号：EP1860062A3

    公开(公告)日：2012-02-22

    申请号：EP07252093.5

    申请日：2007-05-22

    Applicant: STMicroelectronics, Inc.

    Inventor： Bryant, Frank ,  Robinson, Murray

    IPC: B81C1/00

    CPC classification number: B81C1/00119 ,  B81B2203/0315 ,  B81C2201/0109

    Abstract: A microfabricated structure and method of making that includes forming a first layer of material on a substrate, forming patterned sacrificial material having a predetermined shape on the first layer of material, and forming a second layer of material over the first layer and the patterned sacrificial material, which is then removed to form an encapsulated cavity. Ideally, the first and second layers are formed of the same type material. A structural support layer can be added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

    Video and/or audio decompression and/or compression device that shares a memory interface
    157.
    发明公开
    Video and/or audio decompression and/or compression device that shares a memory interface 失效
    视频和音频压缩解压与使用普通内存接口

    公开(公告)号：EP2288168A3

    公开(公告)日：2011-03-09

    申请号：EP10176611.1

    申请日：1997-08-22

    Applicant: STMicroelectronics, Inc.

    Inventor： Diaz, Raul Zegers ,  Owen, Jefferson Eugene

    IPC: H04N7/50 ,  G06F13/362

    CPC classification number: H04N19/423 ,  H04N19/61 ,  H04N21/4143 ,  H04N21/4435

    Abstract: An electronic system coupled to a memory, comprising: a core logic chipset having access to the memory; a decoder having access to the memory; a memory interface coupled to the core logic chipset and the decoder, the memory interface having an arbiter coupled to a core logic chipset direct memory access engine and a decoder direct memory access engine, the arbiter for selectively providing access for the core logic chipset and the decoder to the memory; and a bus coupled to the memory, the first device and the decoder, wherein the decoder and the core logic chipset are coupled to the memory through the bus, the bus having a bandwidth providing access to the memory sufficient to maintain real-time operation of the decoder and to allow the core logic chipset to access the memory thereby enabling the decoder and the core logic chipset to share the memory; wherein said memory interface is operable to provide memory access to the core logic chipset through said bus when the decoder is not operating.

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