-
公开(公告)号：US20180316080A1
公开(公告)日：2018-11-01
申请号：US16028462
申请日：2018-07-06
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takahiro BABA , Kuniaki YOSUI
CPC classification number: H01P3/082 , H01P3/06 , H01P3/085 , H05K1/0225 , H05K1/025 , H05K1/0253 , H05K1/147 , H05K2201/09272 , H05K2201/09281 , H05K2201/09727 , H05K2201/10189
Abstract: A high-frequency signal transmission line includes an element, a linear signal line provided at the element and including a first end and a second end, and at least one ground conductor provided at the element and extending along the signal line. The element includes stacked insulating layers. The ground conductor is positioned opposite to the signal line with the insulating layer positioned therebetween. The ground conductor is a contiguous conductor. The signal line, the ground conductor, and the element generate a characteristic impedance. The signal line includes a first section and a second section. The first section is an uninterrupted section generating a characteristic impedance greater than or equal to a first characteristic impedance at the first end and including the first end. The second section generates a characteristic impedance less than the first characteristic impedance and is adjacent to the first section. The second section is longer than the first section. The signal line is wider in the second section than in the first section.
-
公开(公告)号：US09913376B2
公开(公告)日：2018-03-06
申请号：US15146364
申请日：2016-05-04
Applicant: Northrop Grumman Systems Corporation
Inventor： Anthony L. Long , Alexander Parra, II
CPC classification number: H05K1/144 , H05K1/0237 , H05K1/0243 , H05K1/0253 , H05K1/11 , H05K1/118 , H05K1/141 , H05K1/181 , H05K3/361 , H05K2201/09072 , H05K2201/09281 , H05K2201/09827 , H05K2201/10378 , H05K2201/10886
Abstract: An exemplary bridging inter-connector establishes electrical connections between conductors on a PCB and aligned conductors on a first board mounted to the PCB. A flexible non-conductive sheet covers at least a portion of these conductors. Separated conductive strips on the sheet that are dimensioned to align with and engage at least a portion of both the aligned conductors. A thin film of a bonding agent is disposed on the separated conductive strips and located to engage at least a portion of both aligned conductors to form a conductive connection.
-
公开(公告)号：US09673502B2
公开(公告)日：2017-06-06
申请号：US15285615
申请日：2016-10-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi Sasaki , Nobuo Ikemoto , Shigeru Tago
CPC classification number: H01P3/003 , H01P3/08 , H01P3/085 , H05K1/0225 , H05K1/0253 , H05K1/0284 , H05K1/0393 , H05K1/147 , H05K2201/09245 , H05K2201/09281 , H05K2201/09727
Abstract: A dielectric element assembly includes a plurality of dielectric layers stacked on each other in a direction of lamination and extends in an x-axis direction. A signal line is provided in the dielectric element assembly and extends in the x-axis direction. A reference ground conductor is provided on a positive side in a z-axis direction relative to the signal line. An auxiliary ground conductor is provided on a negative side in the z-axis direction relative to the signal line. Via-hole conductors connect the reference ground conductor and the auxiliary ground conductor and are provided in the dielectric element assembly on the negative side relative to the center in a y-axis direction. A portion of the signal line in a section which includes the via-hole conductors is positioned on the positive side in the y-axis direction relative to another portion of the signal line in a section which does not include the via-hole conductors.
-
公开(公告)号：US20170025730A1
公开(公告)日：2017-01-26
申请号：US15285615
申请日：2016-10-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi SASAKI , Nobuo IKEMOTO , Shigeru TAGO
IPC: H01P3/00
CPC classification number: H01P3/003 , H01P3/08 , H01P3/085 , H05K1/0225 , H05K1/0253 , H05K1/0284 , H05K1/0393 , H05K1/147 , H05K2201/09245 , H05K2201/09281 , H05K2201/09727
Abstract: A dielectric element assembly includes a plurality of dielectric layers stacked on each other in a direction of lamination and extends in an x-axis direction. A signal line is provided in the dielectric element assembly and extends in the x-axis direction. A reference ground conductor is provided on a positive side in a z-axis direction relative to the signal line. An auxiliary ground conductor is provided on a negative side in the z-axis direction relative to the signal line. Via-hole conductors connect the reference ground conductor and the auxiliary ground conductor and are provided in the dielectric element assembly on the negative side relative to the center in a y-axis direction. A portion of the signal line in a section which includes the via-hole conductors is positioned on the positive side in the y-axis direction relative to another portion of the signal line in a section which does not include the via-hole conductors.
Abstract translation: 电介质元件组件包括在层叠方向上彼此堆叠并沿x轴方向延伸的多个电介质层。 信号线设置在电介质元件组件中并沿x轴方向延伸。 参考接地导体相对于信号线在z轴方向的正侧设置。 辅助接地导体相对于信号线设置在z轴方向的负侧。 通孔导体连接参考接地导体和辅助接地导体，并且在y轴方向相对于中心的负侧设置介质元件组件。 包括通孔导体的部分中的信号线的一部分在不包括通孔导体的部分中位于相对于信号线的另一部分的y轴方向的正侧。
-
公开(公告)号：US09480147B2
公开(公告)日：2016-10-25
申请号：US14483749
申请日：2014-09-11
Applicant: LG INNOTEK CO., LTD.
Inventor： Byeong Seob Kim , Ji Sung Ahn
CPC classification number: H05K1/0259 , G06F1/1643 , G06F3/044 , G06F2203/04107 , H05K3/361 , H05K2201/09227 , H05K2201/09272 , H05K2201/09281 , H05K2201/09727
Abstract: A touch window includes a substrate, a sensing electrode on the substrate, a wire electrically connected with the sensing electrode, a ground wire adjacent to the wire, and a printed circuit board connected with the wire and the ground wire. An overlap length between the ground wire and the printed circuit board is longer than an overlap length between the wire and the printed circuit board. Alternatively or simultaneously, a line width of the ground wire is wider than an interval or gap between the wire parallel to the printed circuit.
Abstract translation: 触摸窗包括基板，基板上的感测电极，与感测电极电连接的导线，与导线相邻的接地线以及与导线和接地线连接的印刷电路板。 接地线和印刷电路板之间的重叠长度大于导线和印刷电路板之间的重叠长度。 或者或同时地，接地线的线宽比平行于印刷电路的线之间的间隔或间隙宽。
-
Patent Agency Ranking
156.发明申请公开(公告)号：US20160183386A1
公开(公告)日：2016-06-23
申请号：US14617864
申请日：2015-02-09
Applicant: QUALCOMM Incorporated
Inventor： Young Kyu SONG , Layal ROUHANA , Kyu-Pyung HWANG , Omar James BCHIR
CPC classification number: H05K3/4644 , H01L2224/16225 , H01L2924/15311 , H05K1/0231 , H05K1/0234 , H05K1/0243 , H05K1/0298 , H05K1/111 , H05K1/113 , H05K1/114 , H05K1/115 , H05K1/167 , H05K1/181 , H05K3/1258 , H05K3/321 , H05K3/3442 , H05K3/4697 , H05K2201/0792 , H05K2201/09227 , H05K2201/09281 , H05K2201/09954 , H05K2201/10015 , H05K2201/10636 , H05K2203/0545 , Y02P70/611
Abstract: Methods and apparatus for controlling an equivalent-series resistance (ESR) of a capacitor are provided. An exemplary apparatus includes a substrate having a land side, the capacitor mounted on the land side of the substrate and having both the ESR and terminals, a resistive pattern coupled to the terminals, and a plurality of vias coupled to the resistive pattern. The resistive pattern is configured to control the ESR. The resistive pattern can be formed of a resistive paste. The resistive pattern can be formed in a substantially semicircular shape having an arc ranging from substantially 45 degrees to substantially 135 degrees. The capacitor can be a surface mount device. The resistive pattern can be formed in a shape of a land-side capacitor mounting pad, a via, or both.
Abstract translation: 提供了用于控制电容器的等效串联电阻（ESR）的方法和装置。 示例性装置包括具有接地侧的基板，安装在基板的接地侧上并具有ESR和端子的电容器，耦合到端子的电阻图案以及耦合到电阻图案的多个通孔。 电阻模式被配置为控制ESR。 电阻图案可以由电阻浆料形成。 电阻图案可以形成为具有大致45度至基本上135度的弧度的大致半圆形状。 电容器可以是表面贴装器件。 电阻图案可以形成为陆侧电容器安装垫，通孔或两者的形状。
-
公开(公告)号：US20150289364A1
公开(公告)日：2015-10-08
申请号：US14678039
申请日：2015-04-03
Applicant: Clothing Plus MBU Oy
Inventor： Aino-Maria ILKKO , Heidi MALMIVAARA , Heikki JAAKKOLA , Manu MYRY
CPC classification number: H05K1/0283 , H05K1/0277 , H05K1/028 , H05K1/0296 , H05K1/038 , H05K3/22 , H05K2201/0394 , H05K2201/09036 , H05K2201/09263 , H05K2201/09281 , Y10T29/49218
Abstract: A stretchable device for transmitting signal between end points, such as a sensor and electronic unit, includes a conductive element, which is coupled with a supporting structure by introducing the conductive element successively through the thickness of the supporting structure to the first and second side of the supporting structure, thereby providing a corrugated structure for the conductive element, which is configured to be straighten out at least partially during stretching the device in its longitudinal direction. The conductive element is coupled with the supporting structure between first and second outer layers thereby providing the stretchable device.
Abstract translation: 用于在诸如传感器和电子单元的端点之间传输信号的可拉伸装置包括导电元件，该导电元件通过将导电元件依次通过支撑结构的厚度引导到支撑结构的第一和第二侧而与支撑结构耦合 支撑结构，从而提供用于导电元件的波纹结构，其被构造成在沿纵向拉伸装置期间至少部分地伸直。 导电元件与第一和第二外层之间的支撑结构耦合，从而提供可拉伸装置。
-
公开(公告)号：US20150245469A1
公开(公告)日：2015-08-27
申请号：US14629697
申请日：2015-02-24
Applicant: YAZAKI CORPORATION
Inventor： Hisashi HANAZAKI
CPC classification number: H05K1/0263 , H01B7/0838 , H05K1/0265 , H05K1/028 , H05K1/0293 , H05K1/0393 , H05K1/181 , H05K3/101 , H05K3/102 , H05K3/125 , H05K3/1275 , H05K2201/0305 , H05K2201/09281 , H05K2201/09727 , H05K2201/09736 , H05K2201/10181 , H05K2203/107
Abstract: A flexible flat circuit includes a pair of insulation sheets, and a plurality of conductors that are held between and covered with the pair of insulation sheets in a state that the plurality of conductors are separated to each other. Among from the plurality of conductors, at least conductors with different current capacities are different in thickness to each other.
Abstract translation: 柔性扁平电路包括一对绝缘片，以及多个导体，其以多个导体彼此分离的状态保持在一对绝缘片之间并被其覆盖。 在多个导体中，至少具有不同电流容量的导体的厚度彼此不同。
-
公开(公告)号：US09078360B2
公开(公告)日：2015-07-07
申请号：US14012195
申请日：2013-08-28
Applicant: Ronald Steven Cok
Inventor： Ronald Steven Cok
CPC classification number: H05K1/0274 , H05K1/0298 , H05K1/097 , H05K3/0041 , H05K3/12 , H05K3/1258 , H05K3/1275 , H05K3/1283 , H05K3/1291 , H05K3/465 , H05K3/4685 , H05K2201/09209 , H05K2201/09281 , H05K2201/0979 , H05K2201/09845 , H05K2203/0108
Abstract: An imprinted micro-structure includes a substrate having a first layer in relation thereto. First, second, and third micro-channels are imprinted in the first layer and have first, second, and third micro-wires respectively located therein. A second layer is adjacent to and in contact with the first layer. Imprinted first and second connecting micro-channels including first and second connecting micro-wires are in contact with the first and second micro-wires respectively and are isolated from the third micro-wire. A third layer is adjacent to and in contact with the second layer and has an imprinted bridge micro-channel with a bridge micro-wire contacting the first and second connecting micro-wires and separate from the third micro-wire so that the first and second micro-wires are electrically connected and electrically isolated from the third micro-wire.
Abstract translation: 压印的微结构包括具有与之相关的第一层的衬底。 第一，第二和第三微通道印在第一层中，并且分别位于其中的第一，第二和第三微细线。 第二层与第一层相邻并与第一层接触。 包括第一和第二连接微线的印刷的第一和第二连接微通道分别与第一和第二微线接触并与第三微线隔离。 第三层与第二层相邻并与第二层接触，并且具有印刷桥微通道，桥接微线与第一和第二连接微线接触并与第三微线分离，使得第一和第二 微线电连接并与第三微线电隔离。
-
公开(公告)号：US20140104802A1
公开(公告)日：2014-04-17
申请号：US14050258
申请日：2013-10-09
Applicant: Renesas Electronics Corporation
Inventor： Ryuichi Oikawa
IPC: H05K1/18
CPC classification number: H05K1/18 , H01L21/4857 , H01L21/486 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/64 , H01L23/66 , H01L2223/6616 , H01L2223/6638 , H01L2224/16225 , H01L2224/49171 , H01L2924/00 , H01L2924/13091 , H01L2924/15311 , H01L2924/30111 , H05K1/0219 , H05K1/0225 , H05K1/0236 , H05K1/0245 , H05K1/0248 , H05K1/0251 , H05K3/429 , H05K3/4602 , H05K2201/09227 , H05K2201/09281 , H05K2201/096 , H05K2201/09627 , H05K2201/10734
Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.
Abstract translation: 半导体器件包括半导体芯片，多个外部端子和基板。 电路板包括：第一主表面，其中形成电连接到半导体芯片的多个第一电极;第二主表面，其中形成有多个与多个外部端子电连接的第二电极;以及多个互连 层，设置在第一主表面和第二主表面之间，用于形成电连接第一电极和与其对应的第二电极的多个信号路径。 互连层包括多个金属构件，其分散配置在比构成信号路径的信号的信号频带的电磁波长短的距离处，在其附近形成用于形成的互连的结构部分 信号路径被改变。
-
-
-
-
-
-
-
-
-
Search Results
312
records
(took 0.027 seconds)
