公开(公告)号：EP1320288A3

公开(公告)日：2004-10-13

申请号：EP02255035.4

申请日：2002-07-17

Applicant: FUJITSU LIMITED

Inventor： Kikuchi, Shunichi, c/o Fujitsu Limited ,  Yamada, Mitsutaka, c/o Fujitsu Limited ,  Iketaki, Kenji, c/o Fujitsu Limited

IPC: H05K3/34 ,  H05K1/02

CPC classification number: H05K1/0209 ,  H05K1/0201 ,  H05K3/3494 ,  H05K2201/066 ,  H05K2201/09781 ,  H05K2201/10204 ,  H05K2203/1121 ,  H05K2203/304 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A printed wiring board device (10) includes circuit parts (20) which are mounted on a wiring board and constitute parts of a circuit in the printed wiring board device (10). Pads (22) are provided on the wiring board around the circumference of the circuit parts (20), the pads (22) being electrically isolated from the circuit. Heat-absorbing dummy parts (30) are mounted on the pads (22), and the dummy parts (30) absorb heat from the circuit parts (20) through the pads (22) during reflow soldering.

Abstract translation: 印刷线路板装置（10）包括安装在布线板上并构成印刷线路板装置（10）中的电路的一部分的电路部分（20）。 在电路部件（20）周围的布线板上设置有焊盘（22），焊盘（22）与电路电绝缘。 吸热虚拟部件（30）安装在焊盘（22）上，并且虚拟部件（30）在回流焊接期间通过焊盘（22）从电路部件（20）吸收热量。

公开(公告)号：EP1377139A1

公开(公告)日：2004-01-02

申请号：EP03011098.5

申请日：2003-05-21

Applicant: ORION ELECTRIC CO., Ltd.

Inventor： Kazuyuki, Nagata

IPC: H05K1/02

CPC classification number: H05K1/0266 ,  H05K1/0295 ,  H05K1/18 ,  H05K2201/09936 ,  H05K2201/09954 ,  H05K2201/10015 ,  H05K2201/10174 ,  H05K2201/10204 ,  H05K2201/10522 ,  H05K2203/168

Abstract: Disclosed is a foolproof polarity indication of poled electronics parts or devices to be given to a printed circuit board to assure that poled electronics parts and/or devices be correctly mounted in respect of their polarities to meet occasional requirements dependent on different specifications. Each pair of terminal holes (1a,1b) are allotted to a given poled electronics part or device. Two symbols (2a,2b) representative of such electronics part or device are arranged side by side on either side of the line drawn from one to the other terminal hole. The poled electronics part or device symbols are of reversed polarities. This dual symbol arrangement is effective to draw workers' attention in mounting electrode components in terms of their polarities. When extra components (S) or dummy ones are combined with such a poled component, they are encircled by a boundary line (6), thereby showing the correct polarity direction of the poled component in respect of whether it is enclosed or not.

Abstract translation: 公开的是必须考虑到印刷电路板，以确保没有极化电子部件和/或装置被正确地安装在相对于它们的极性，以满足依赖于不同规格的偶然要求极化电子部件或装置的万无一失极性指示。 每一对端子孔（1A，1B）被分配给一个给定的极化电子部分或装置。 两个符号（2A，2B）代表寻求电子部分或装置被并排布置在从一个绘制到另一端孔的线的两侧。 极化的电子部件或装置的符号反转极性。 这双符号设置可有效吸引工人的注意力，在它们的极性方面安装电极组件。 当附加组件（S）或虚设那些与寻求极化组分组合，它们由边界线（6）包围，从而示出在关于它是否被封闭或不极化分量的正确的极性方向。

公开(公告)号：EP1098368A1

公开(公告)日：2001-05-09

申请号：EP00915469.1

申请日：2000-04-11

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： KIMURA, Suzushi ,  HIMORI, Tsuyoshi ,  HASHIMOTO, Koji

IPC: H01L25/00 ,  H01L23/12 ,  H01L21/56 ,  H05K1/18 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/184 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/19103 ,  H01L2924/19105 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4046 ,  H05K3/4602 ,  H05K2201/09118 ,  H05K2201/09827 ,  H05K2201/10204 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/161 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49172

Abstract: The invention relates to a module component having chip components buried in a circuit board, and a method of manufacturing the same, and more specifically it relates to a module component capable of obtaining desired circuit characteristics and functions stably if the size of the component is reduced, being produced very efficiently, and suited to machine mounting, and a method of manufacturing the same. According to the invention, since a desired circuit is composed by disposing a specific number of chip components according to a specified rule, it is not necessary to heat the buried chip components at high temperature when forming a module, chip components are obtained in specified values, and the circuit characteristics, functions, and dimensional precision are stably obtained exactly as designed, and moreover since the chip components are disposed according to a specified rule, it is easy to automate insertion of chip components and increase its operation speed, even if the size of the chip components is reduced, and the circuit composition may be flexibly and easily changed only by changing the inserting position and type of chip components.

Abstract translation: 本发明涉及具有埋在电路板中的芯片部件的模块部件及其制造方法，更具体地说，涉及一种能够获得希望的电路特性并且如果部件尺寸减小则能够稳定地工作的模块部件 ，非常有效地生产并且适合于机器安装，以及其制造方法。 根据本发明，由于根据规定通过设置特定数量的芯片部件来构成所需的电路，因此在形成模块时不需要在高温下加热埋入芯片部件，在特定值中获得芯片部件 ，并且电路特性，功能和尺寸精度均按设计得到稳定的获得，而且由于芯片部件按照规定进行配置，因此即使是在芯片部件的插入和提高其运行速度的情况下也容易， 芯片部件的尺寸减小，并且仅通过改变芯片部件的插入位置和类型可以灵活且容易地改变电路组成。

公开(公告)号：EP0461989B1

公开(公告)日：1993-09-15

申请号：EP91401535.9

申请日：1991-06-11

Applicant: TONNA ELECTRONIQUE

Inventor： Bour, Gilles

IPC: H05K7/20

CPC classification number: H05K1/0209 ,  H01L23/433 ,  H01L2924/0002 ,  H05K2201/066 ,  H05K2201/09781 ,  H05K2201/10166 ,  H05K2201/10204 ,  H01L2924/00

公开(公告)号：EP0461989A1

公开(公告)日：1991-12-18

申请号：EP91401535.9

申请日：1991-06-11

Applicant: TONNA ELECTRONIQUE

Inventor： Bour, Gilles

IPC: H05K7/20

CPC classification number: H05K1/0209 ,  H01L23/433 ,  H01L2924/0002 ,  H05K2201/066 ,  H05K2201/09781 ,  H05K2201/10166 ,  H05K2201/10204 ,  H01L2924/00

Abstract: La présente invention concerne un dispositif comprenant des composants électroniques montés en surface, caractérisé par le fait qu'il comprend un élément (305, 405) en matériau diélectrique placé entre une connexion (304) d'un composant monté en surface (302) et un élément radiateur, pour assurer la fonction de shunt thermique entre ceux-ci.

Abstract translation: 本发明涉及一种装置，其包括表面安装的电子元件，它DASS包括介电材料元件（305，405）的表面安装部件（302）的连接（304）之间放置并在耗散元件 为了保证它们之间的热分流。

公开(公告)号：US20240007551A1

公开(公告)日：2024-01-04

申请号：US18230027

申请日：2023-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bowoong SEO ,  Hokyung Kang ,  Yongwoon Kim ,  Jonghoon Woo ,  Jinwan An

IPC: H04M1/02 ,  H05K1/02 ,  H05K1/11

CPC classification number: H04M1/0216 ,  H05K1/028 ,  H05K1/118 ,  H05K1/115 ,  H05K2201/05 ,  H05K2201/10128 ,  H05K2201/10151 ,  H05K2201/10204

Abstract: A foldable electronic device includes a display including a first and second areas; a first and second housings; a hinge structure foldably connecting the first housing and the second housing to each other on a folding axis; a flexible printed circuit board (FPCB) extending across the folding axis from a first space between the first housing and the display to a second space between the second housing and the display and including a first bending portion and a second bending portion; a sensor configured to identify an impedance in the FPCB; and a processor configured to identify a folding angle between the first housing and the second housing based on the impedance. The first bending portion includes a first sensing pattern part including a first pattern forming a first electrical path and a second pattern forming a second electrical path.

公开(公告)号：US09812387B2

公开(公告)日：2017-11-07

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/16 ,  H05K7/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H05K3/36 ,  H05K3/00 ,  H05K3/22 ,  H05K3/40 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

公开(公告)号：US09748023B2

公开(公告)日：2017-08-29

申请号：US14811848

申请日：2015-07-29

Applicant: GNE TECH CO., LTD.

Inventor： Jae Ku Kim

IPC: H01B17/14 ,  H05K3/42 ,  H05K3/00 ,  G02F1/1345 ,  H05K1/02 ,  H05K1/11 ,  H01B19/00 ,  H05K3/34 ,  C23F1/02 ,  C23F1/18

CPC classification number: H01B17/14 ,  B81C2203/054 ,  C23F1/02 ,  C23F1/18 ,  G02F1/13452 ,  H01B19/00 ,  H05K1/02 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/3442 ,  H05K3/42 ,  H05K2201/10204 ,  H05K2201/2036 ,  Y10T29/303 ,  Y10T29/49227 ,  Y10T428/24488 ,  Y10T428/31678

Abstract: Disclosed is a method for manufacturing a substrate gap supporter. The method includes: a first step of forming metal foils on both sides of an insulating plate; a second step of etching the metal foils to expose the insulating plate so that a plurality of stripes are arranged on both sides of the insulating plate in parallel at constant intervals, wherein the stripes expose the insulating plate at constant widths; and a third step of cutting in direction in parallel with the stripes and in direction in vertical with the stripes along one edges of the stripes to complete the gap supporter.

公开(公告)号：US20170131586A1

公开(公告)日：2017-05-11

申请号：US15318532

申请日：2015-06-19

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masaki NAKAYAMA ,  Motoji Shikota ,  Takashi Matsui ,  Yashuhiko Tanaka ,  Hiroki Miyazaki

IPC: G02F1/1345 ,  H01L23/31 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02

CPC classification number: G02F1/13452 ,  G02F1/13454 ,  H01L23/3142 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0306 ,  H05K1/181 ,  H05K3/305 ,  H05K3/323 ,  H05K2201/09781 ,  H05K2201/10136 ,  H05K2201/10204 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2924/00

Abstract: An array circuit board 11B includes a glass substrate, an IC chip 20, two ACFs 30, and a resin film 32. The IC chip 20 is disposed on the glass substrate. The ACFs 30 are disposed between the glass substrate and the IC chip 20 for electrically connecting the glass substrate and the IC chip 20 together. The ACFs 30 are separated from each other. The resin film 32 is made of resin material having cure shrinkage smaller than the ACFs 30 and disposed to fill a gap between the ACFs 30 adjacent to each other between the glass substrate and the IC chip 20.

公开(公告)号：US20170019993A1

公开(公告)日：2017-01-19

申请号：US14798384

申请日：2015-07-13

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/22 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

Abstract translation: 本公开涉及半导体衬底，半导体模块及其制造方法。 半导体衬底包括第一电介质结构，第二电介质结构，第一图案化导电层和第二图案化导电层。 第一电介质结构具有与第一表面相对的第一表面和第二表面。 第二电介质结构具有与第三表面相对的第三表面和第四表面，其中第四表面与第一表面相邻。 第二电介质结构限定了从第三表面延伸到第四表面的通孔。 空腔由通孔和第一电介质结构限定。 第一图案化导电层设置在第一电介质结构的第一表面上。 第二图案化导电层设置在第一介电结构的第二表面上。