公开(公告)号：EP2348634B1

公开(公告)日：2014-03-19

申请号：EP10197058.0

申请日：2010-12-27

Applicant: STMicroelectronics Srl ,  STMicroelectronics Pvt. Ltd.

Inventor： Veggetti, Andrea Mario ,  Jain, Abhishek ,  Rohilla, Pankaj

IPC: H03K3/037 ,  H03K3/356 ,  H03K19/00

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

公开(公告)号：EP2385484A1

公开(公告)日：2011-11-09

申请号：EP10305478.9

申请日：2010-05-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Pvt. Ltd

Inventor： Chotard, Ludovic ,  Sanches, Michel ,  Schwambach, Vitor ,  Chandra, Mahesh

IPC: G06K9/00

CPC classification number: G06K9/00228 ,  G06K9/6257

Abstract: The invention concerns a method of performing, by an image processing device, object detection in an image comprising: performing one or more tests of a test sequence for detection of a first object on pixels values of a plurality of at least partially overlapping sub-regions (310, 312, 314) of a first search window (108); generating a cumulative score based on results of said one or more tests on said plurality of sub-regions; comparing said cumulative score with a threshold value; and based on said comparison, selectively performing one or more tests of said test sequence on at least one further sub-region of said first search window, said at least one further sub-region at least partially overlapping each of said plurality of sub-regions.

Abstract translation: 本发明涉及一种通过图像处理装置执行图像中的对象检测的方法，包括：对多个至少部分重叠的子区域的像素值执行用于检测第一对象的测试序列的一个或多个测试 （108,312）的第一搜索窗口（310,312,314）; 基于对所述多个子区域的所述一个或多个测试的结果生成累积分数; 将所述累积分数与阈值进行比较; 并且基于所述比较，在所述第一搜索窗口的至少一个另外的子区域上选择性地执行所述测试序列的一个或多个测试，所述至少一个另外的子区域至少部分地与所述多个子区域中的每一个子区域重叠 。

公开(公告)号：EP1677175A3

公开(公告)日：2011-05-04

申请号：EP05113079.7

申请日：2005-12-29

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Uguen, Laurent ,  Dhiman, Gaurav ,  Kapoor, Gaurav

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

Abstract: A system for dynamic power management in a distributed architecture system on chip, comprising a means for dynamically defining the feasibility of entering a low power mode of operation based on the status of components of the system, a means for entering or exiting safely from a low power state based on said feasibility, a means for decreasing the power centric communication between various processors and a means for increasing the low power mode time. Thus a framework is proposed in the instant invention wherein all the device drivers dynamically maintain the information on the feasibility of a low power transition at any point of time. Thus whenever an opportunity to enter a low power mode comes up one has to just check this feasibility variable to determine whether the low power mode entry is viable or not. For ensuring the safe transition to a low power mode, a stalling machine is proposed in case of DSPs. For further saving power, a power centric communication channel is established between various processors and to reduce the load on this communication channel techniques like quad-ring buffer and DSP feedback are proposed.

公开(公告)号：EP1653747A3

公开(公告)日：2009-06-17

申请号：EP05022773.5

申请日：2005-10-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kaushik, Saha ,  Chakraborty, Chiranjib ,  Chatterjee, Subrata

IPC: H04N7/62

CPC classification number: H04N21/4305

Abstract: A system for clock recovery in digital video communication comprising a delay measurement block for generating PCR input signals and for continuously determining time interval between successive PCR input signals, a first storage device for generating a first PCR signal corresponding to said time interval between arrival of successive PCR input signals, a PCR inter-arrival time computation filtering device for determining the average time of arrival difference between successive PCR packets. An error correction device for minimizing the error in the average PCR difference between successive PCR packets, a controlled system clock generator connected to the output of said error correction device to generate system clock, a second storage device for generating a first system clock output, a controlled clock period difference computation element for computing the clock period difference between said first and second system clock output, and said controlled clock period difference computation element is coupled at its output to said error correction device to form a feedback circuit for minimizing the error between said system clock output and successive PCR differences observed.

公开(公告)号：EP1672791A3

公开(公告)日：2008-09-17

申请号：EP05112285.1

申请日：2005-12-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Tiwari, Naveen ,  Singh, Balwant

IPC: H03K3/03

CPC classification number: G06F1/04 ,  H03K3/0315 ,  H03K3/70

Abstract: A glitch free controlled ring oscillator comprising a programmable delay chain (1) connected to a gating and inverting means (3) wherein a latching means (2) is provided between said prgrammable delay chain (1) and said gating and inverting means (3) for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to said registered clock state.

公开(公告)号：EP1742229A3

公开(公告)日：2008-05-21

申请号：EP06115639.4

申请日：2006-06-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Dubey, Prashant ,  Kashyap, Amit

IPC: G11C29/00

CPC classification number: G11C29/802 ,  G11C29/4401 ,  G11C29/812

Abstract: The present invention provides a built-in self-repairable memory. The invention repairs the faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses lesser number of fuses to actually make a perfect repair and thus result into a yield enhancement. The fuse data is stored in a compressed form and then decompressed at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area).

公开(公告)号：EP1727156A3

公开(公告)日：2008-04-09

申请号：EP06114150.3

申请日：2006-05-18

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： DUBEY, Prashant

IPC: G11C29/02

CPC classification number: G11C29/02 ,  G11C5/025 ,  G11C29/024 ,  G11C2029/1206

Abstract: The invention provides an integrated test device thereby reducing external wiring congestion to the memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.

公开(公告)号：EP1901430A2

公开(公告)日：2008-03-19

申请号：EP07114839.9

申请日：2007-08-23

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Srivastava, Ankit ,  Jandial, Sourav

IPC: H03K19/0185

CPC classification number: H03K19/018528 ,  H03K3/012 ,  H03K3/356165 ,  H03K3/356182

Abstract: The present invention provides a level shifter circuit capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS devices, when the input signal switches from a high logic level to a low logic level. The dynamic charge injection device is incorporated at output nodes to provide initial thrust to the level shifter circuit, which triggers a positive regenerative feedback of cross-coupled pull up PMOS devices enabling a rapid transition and hence the high frequency operations.

Abstract translation: 本发明提供了一种能够进行高频操作的电平移位器电路。 当输入信号从高逻辑电平切换到低逻辑电平时，电平移位器电路利用动态电荷注入器件，其减小输入NMOS器件的栅极和漏极之间的电容耦合效应。 动态电荷注入器件集成在输出节点上，为电平转换器电路提供初始推力，触发交叉耦合上拉PMOS器件的正向再生反馈，从而实现快速转换，从而实现高频操作。

公开(公告)号：EP1330033A3

公开(公告)日：2006-11-29

申请号：EP03000105.1

申请日：2003-01-02

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chauhan, Rajat ,  Kaushik, Rajesh

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: This invention provides a method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

公开(公告)号：EP1708080A1

公开(公告)日：2006-10-04

申请号：EP06111980.6

申请日：2006-03-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Bahl, Swapnil ,  Singh, Balwant

IPC: G06F5/10

CPC classification number: G06F5/10 ,  G06F2205/063

Abstract: The present invention provides a configurable length First-in First-out memory comprising a memory core for storing the data; a write address counter connected to said memory core for counting the locations for writing the data; and a read address counter connected to said memory core for counting the locations for reading the data wherein said read address counter includes a comparator for generating synchronous reset for said read address counter and a selection means connected to said comparator for selecting user defined FIFO length or pre-programmed write address counter length.

Abstract translation: 本发明提供了一种可配置长度的先进先出存储器，包括用于存储数据的存储器核心; 连接到所述存储器核心的写入地址计数器，用于对用于写入数据的位置进行计数; 以及连接到所述存储器核心的读地址计数器，用于对用于读取数据的位置进行计数，其中所述读地址计数器包括用于为所述读地址计数器产生同步复位的比较器，以及连接到所述比较器的选择装置，用于选择用户定义的FIFO长度或 预编程写地址计数器长度。