公开(公告)号：JP2000299425A

公开(公告)日：2000-10-24

申请号：JP10854499

申请日：1999-04-15

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KAN SORYU ,  KO MEIKO

IPC: H01L21/66 ,  H01L21/98 ,  H01L23/12 ,  H01L23/31 ,  H01L23/538

Abstract: PROBLEM TO BE SOLVED: To restore a chip module by replacing a faulty chip or conductor with a normal chip or conductor when a faulty area is discovered by carrying out performance tests, after the chip is stuck to a package substrate provided with solder pads and solder pads for restoration, and electrically connected to the solder pads through conductors. SOLUTION: Pluralities of first solder pads 302a, second solder pads 302b, and contacts 304 are provided on a package substrate 300. The first solder pads 302a are arranged in the periphery of the proposed sticking position of a chip 308, and the second solder pads 302b are arranged in the peripheral edge section of the substrate 300 correspondingly to the first solder pads 302a. The solder pads 302a and 302b are electrically connected to their corresponding contacts 304 through contact pins 306. Then, after the chip 308 is fixed to the upper surface 318a of the package substrate 300 by using an insulating adhesive or adhesive tape, the solder pads on the chip 308 are electrically connected to the first solder pads 302a through wire-bonded conductors 310.

公开(公告)号：JP2000277472A

公开(公告)日：2000-10-06

申请号：JP8261899

申请日：1999-03-25

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN GAKUCHU

IPC: H01L21/304 ,  B24B37/013 ,  B24B49/04 ,  B24B49/12 ,  G01B11/06 ,  G01N17/00 ,  H01L21/3105 ,  B24B37/04

Abstract: PROBLEM TO BE SOLVED: To detect the thickness of an insulating layer by, when a reflected light is measured using the incident light emitted to a material layer, integrating the intensity of reflected light along a time axis, and dividing the integration value by a product of the differential value of reflected light intensity and polishing time. SOLUTION: While a material layer is polished in chemical/mechanical polishing, a material is continuously irradiated with a laser beam as incident light. The reflected light is condensed to record its intensity, and the recorded intensity is integrated/differentiated for time. the integrated value of the intensity divided by the product of the differential value of intensity and time to provide an I-Dt curve, so that the peak 308-316 of the curve reflects a peculiar thickness value of the material layer. Thus, the intensity peak and bottom of the reflected light is accurately discriminated on the I-Dt curve for detecting the thickness of an insulating layer.

公开(公告)号：JP2000228087A

公开(公告)日：2000-08-15

申请号：JP2794099

申请日：1999-02-04

Applicant: UNITED MICROELECTRONICS CORP

Inventor： JO SHINKYU

IPC: G11C11/41

Abstract: PROBLEM TO BE SOLVED: To obtain a dual port random access memory(RAM) using a symmetrical layout in which performance is improved to increase recording density. SOLUTION: A dual port random access memory comprises four NMOS transistors NM11-14 and four PMOS transistors PM11-14. The NMOS transistors NM11-14 and the PMOS transistors PM11-14 both are used as a pass gate. In more detail, two NMOS transistors are used as a pass gate of one group of bit line, two PMOS transistors are used as a pass gate of another group of bit line.

公开(公告)号：JP2000225558A

公开(公告)日：2000-08-15

申请号：JP2892299

申请日：1999-02-05

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN GAKUCHU

IPC: B24B37/22 ,  B24D3/34 ,  B24D13/12 ,  B24D13/14 ,  H01L21/304 ,  B24B37/00

Abstract: PROBLEM TO BE SOLVED: To provide a polishing pad used in the chemical-mechanical polishing process for a semiconductor board and furnished with a pad body and an indication part to clearly indicate the degree of wear of the pad body. SOLUTION: To a polishing pad 20, slurry is supplied during the chemical- mechanical polishing process so as to polish a wafer. The degree of wear of the polishing pad 20 progresses in the course of the polishing process, and when the serviceable limit is approached or attained to require replacement of the pad in service with a new one, the hue of the indication part 22 and/or the slurry varies. This allows the operator to know that replacement should take place to led to prevention of an item polished from being damaged resuiting from the use of a poorly conditioned pad, enhancement of the product quality, heightening of the yield, and reduction of the manufacturing costs.

公开(公告)号：JP2000223651A

公开(公告)日：2000-08-11

申请号：JP2226499

申请日：1999-01-29

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SEN MEICHI ,  RIN SEITOKU

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To reduce thickness and surface area by providing a lead frame with a die pad and several leads each having inner and outer lead parts. SOLUTION: A lead frame being used as a film carrier has a die pad 50 and a plurality of leads 56 each constituting inner and outer leads 52, 54. Chips 58, 60, 62, 64, 66 having faces 58a-66a arranged with a plurality of pads 68 on the die pad 50 are contained in one package having volume substantially equal to the total volume of all chips 58-66 which are then wire bonded to the lead frame. According to the structure, a thin package for facing multichip having small surface area can be obtained.

公开(公告)号：JP2000208736A

公开(公告)日：2000-07-28

申请号：JP815899

申请日：1999-01-14

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHU SHIKUN ,  CHIN KONAN ,  RIN KAKUKI ,  KO KOKUTAI ,  SHA BUNEKI ,  YU SUIYO

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/203 ,  H01L21/768 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To shorten the time required for manufacturing the lower electrode in a DRAM capacitor. SOLUTION: In this method for manufacturing the lower electrode in a DRAM capacitor, a polysilicon is vapor-deposited in place of an amorphous silicon to manufacture a lower electrode 250b. The vapor-deposition temperature of the polysilicon is higher than that for amorphous silicon, so that the vapor- deposition rate of the polysilicon becomes higher than that of amorphous silicon and its vapor-deposition time is shortened greatly. After the formation of polysilicon lower electrode, an ion group 270 is bombarded on a polysilicon layer to destroy the inner structure of the polysilicon layer, so as to change the upper part thereof into an amorphous silicon layer 252a. Finally, by forming a semispherical grain silicon 290 on the lower electrode, the surface area of the lower electrode is increased.

公开(公告)号：JP2000206672A

公开(公告)日：2000-07-28

申请号：JP828299

申请日：1999-01-14

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN KINRYU ,  KO YOSHIN

IPC: H01L21/027 ,  G03F1/26 ,  G03F1/48 ,  G03F1/68 ,  G03F1/08 ,  G03F1/14

Abstract: PROBLEM TO BE SOLVED: To provide a dual photomask used in photolithography in the case of producing an integrated circuit and capable of performing double exposure operation on a semiconductor wafer without mask tooling. SOLUTION: This dual photomask 10 is equipped with a reticle glass plate 12 where a phase shift mask(PSM) chrome area 14 and a binary (BIN) chrome area 16 are adjacently arranged. When the photomask 10 is used, it is shifted between two previously decided positions that a pattern from the area 16 can be transferred to a wafer at the first position and the pattern from the area 14 can be transferred at other position. An exposure scanner is used to expose the wafer through the photomask 10. By this photomask 10, a defect such as the positional deviation of pattern transfer occurring because two masks are used in the case of the conventional technique is eliminated, further yield is improved and the production cost of the wafer is reduced.

公开(公告)号：JP2000195951A

公开(公告)日：2000-07-14

申请号：JP37406198

申请日：1998-12-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO MASUTAMI ,  YU SUIYO

IPC: H01L21/768 ,  H01L21/28

Abstract: PROBLEM TO BE SOLVED: To prevent a group of metallic atoms from spreading into a dielectric layer deposited on the sidewall of a double damask hole by forming an isometric barrier/an adhesive layer prior to performing the RIE treatment for exposing a metallized layer. SOLUTION: After formation of a double damask hole to expose a superposed layer 204, first an isometric barrier / an adhesive layer 216 is made, covering the whole sidewall of the double damask hole, in such a way as not to stop the double damask layer. Next, the bottom of the isometric barrier / adhesive layer 216 lying on the bottom of the double damask hole, and subsequently, the underlying section of the superposed layer 204 is removed until the metallized layer 204 is exposed by anisotropic etching processing. Lastly, conductive material 218 such as copper or the like is deposited on the residual cavity section of the double damask hole. The double damask structure is constituted of the combination of the deposited conductive material 218 and the residual section of the isotropic barrier / the adhesive layer within the double damask hole.

公开(公告)号：JP2000036572A

公开(公告)日：2000-02-02

申请号：JP30433098

申请日：1998-10-26

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIOU FU-TAI ,  RO KATETSU

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To improve the flatness of an integrated circuit by hydrogen-treating a heat resistant metal oxide deposited by using a hydrogen plasma or hot hydrogen, and altering non-electric conductivity of the treated metal oxide to electric conductivity. SOLUTION: A heat resistant metal oxide layer hydrogen-treated by using a hydrogen plasma or hot hydrogen and exposed is converted into a conductive layer. Heat resistant metal oxide layers 116b1 116b2 exposed by the hydrogen- treatment are converted into conductive layers. Meanwhile, non-exposed heat resistant metal oxide layer 116a is still retained in a state of a non-conductive layer. A second conductive layer is formed on the metal oxide layer, and then patterned. As a result an upper surface of an upper electrode 118a of a capacitor 120 and first and second contact mutual connectors 121, 122 become the same relative heights. Thus, the smoothness (flatness) of the integrated circuit can be improved.

公开(公告)号：JP2000019715A

公开(公告)日：2000-01-21

申请号：JP26375898

申请日：1998-09-17

Applicant: UNITED MICROELECTRONICS CORP

Inventor： BENJAMIN ZU MIN RIN

IPC: H01L21/027 ,  G03F1/29 ,  G03F1/30 ,  G03F1/32 ,  G03F1/68 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a photomask capable of enhancing the degree of integration of an IC device. SOLUTION: This double-sided photomask is equipped with two complementary pattern layers formed on respective surfaces of a transparent substrate 700. The two complementary pattern layers are combined into a complete pattern. The two complementary pattern layers are separately formed on different surfaces. In the event of a phase shift photomask, the double-sided photomask is equipped with a phase shift layer.