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    163.
    发明专利
    未知

    公开(公告)号：DE69820246D1

    公开(公告)日：2004-01-15

    申请号：DE69820246

    申请日：1998-07-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/10 ,  G11C16/28 ,  G11C7/00 ,  G11C16/06

    Abstract: A method for reading a non-volatile memory, comprising the steps of: providing a first random memory reading cycle; performing, at the end of the random reading cycle, a collective page precharge; subsequently performing a reading cycle of the page or random type, depending on whether the subsequent reading must be performed within the same page or not; and if a page reading cycle is performed, executing, when the data item is captured, a page precharge step in preparation both for page reading and for random reading.

    165.
    发明专利
    未知

    公开(公告)号：DE69626625D1

    公开(公告)日：2003-04-17

    申请号：DE69626625

    申请日：1996-04-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C29/00 ,  G11C29/44 ,  G06F11/00

    Abstract: A method for detecting redunded defective addresses in a memory device with redundancy comprising at least one memory register (RR1-RRn;RR1'-RRn') for storing at least one defective address. The memory register comprises a plurality of memory units (MU0-MU10) each one storing a defective address bit and comparing the defective address bit with a respective current address bit (A0-A10) supplied to the memory device; the memory register activates a respective redundancy selection signal (RS1-RSn;RSA1-RSAn,RSB1-RSBn) when the current address coincides with the defective address stored therein. The method provides for: activating a forcing signal (F) for forcing the activation of the redundancy selection signal to be independent of the coincindence of a first group (A0-A3) of current address bits, associated to a respective first group (G2) of the memory units, with the defective address bits stored in the respective first group (G2) of memory units; scanning all the possible configurations of a second group (A4-A10) of current address bits associated to a second group (G1) of the memory units and sequentially supplying the memory device with all the configurations; detecting a configuration of the second group (A4-A10) of current address bits for which the redundancy selection signal is activated; while supplying the memory device with the configuration of the second group (A4-A10) of current address bits, deactivating the forcing signal and sequentially supplying the memory device with a scanning of all the possible configurations of the first group (A0-A3) of address bits; detecting a configuration of the first group (A0-A3) of current address bits for which the redundancy selection signal is activated.

    166.
    发明专利
    未知

    公开(公告)号：DE69626099D1

    公开(公告)日：2003-03-13

    申请号：DE69626099

    申请日：1996-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/06 ,  G11C16/28

    Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure (2) that has two output nodes (OUT-L, OUT-R) and has the particularity that it comprises an equalization transistor (7) of a first polarity that is adapted to equalize the two output nodes (OUT-L, OUT-R) and is connected between a first branch (8) and a second branch (9), in which the output nodes are arranged; the equalization transistor (7) is driven by an equalization signal (EQ) whose slope can be modulated as a function of the conductivity of the memory cell of the memory device involved in the reading operation.

    167.
    发明专利
    未知

    公开(公告)号：DE69625582D1

    公开(公告)日：2003-02-06

    申请号：DE69625582

    申请日：1996-03-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO

    IPC: G11C7/10 ,  G11C7/00

    Abstract: A non-volatile memory device (1) having optimized management of data transmission lines, having the particularity that it comprises at least one bidirectional internal bus (3) that runs from one end of the memory device to the other, one or more source structures (5', 5'') that lie externally and internally to the memory device (1), and timer means (8); the timer means (8) are adapted to time-control the independent and exclusive access of the external and internal source structures (5', 5''), within a same memory cycle, to the internal bus (3) for the transmission of data, controls, and functions, from one end of the memory (1) to the other over the internal bus (3).

    168.
    发明专利
    未知

    公开(公告)号：DE69625327D1

    公开(公告)日：2003-01-23

    申请号：DE69625327

    申请日：1996-03-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  FONTANA MARCO ,  BARCELLA ANTONIO

    IPC: G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C7/00

    Abstract: A non-volatile memory device, having the particularity that it comprises an internal bus (3) for the transmission of data and other information of the memory to output pads (4); timer means (8); and means (5, 5') for enabling/disabling access to the internal bus; the timer means (8) time the internal bus to transmit information signals of the memory device that originate from local auxiliary lines (7) over the internal bus (3) when the bus is in an inactive period during a normal memory data reading cycle; the timer means (8) drive the enabling/disabling means (5, 5') to allow/deny access to the internal bus (3) on the part of the information signals or of the data from or to the memory.

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