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公开(公告)号：US20160249456A1
公开(公告)日：2016-08-25
申请号：US14993523
申请日：2016-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jonghyeok YOUN , Jaehyung CHO , Myungkyoon CHUNG
IPC: H05K1/18
CPC classification number: H05K1/115 , H05K1/0216 , H05K2201/09609 , H05K2201/09636
Abstract: An electronic device with a reduced noise may include a printed circuit board and a signal creating unit mounted on the printed circuit board and configured to create at least one signal. The electronic device may also include at least one power via configured to connect a power terminal of the signal creating unit with a main power line disposed in the printed circuit board. The electronic device further includes at least one ground via configured to connect a ground terminal of the signal creating unit with a main ground disposed in the printed circuit board. In this electronic device, the ground via is disposed in parallel with the power via.
Abstract translation: 具有降低噪声的电子设备可以包括印刷电路板和安装在印刷电路板上并被配置为创建至少一个信号的信号产生单元。 电子设备还可以包括至少一个功率通路，其被配置为将信号生成单元的电源端子与布置在印刷电路板中的主电力线连接。 电子设备还包括至少一个接地通路，其经配置以将信号产生单元的接地端与设置在印刷电路板中的主地相连。 在该电子设备中，接地通孔与电源通路并联设置。
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162.发明授权公开(公告)号：US09192044B2
公开(公告)日：2015-11-17
申请号：US13862038
申请日：2013-04-12
Applicant: CANON KABUSHIKI KAISHA
Inventor： Seiji Hayashi , Takuya Kondo , Shoji Matsumoto
CPC classification number: H05K1/0216 , H01L23/49827 , H01L23/49838 , H01L2224/48227 , H05K1/0228 , H05K1/0242 , H05K1/0298 , H05K1/11 , H05K1/114 , H05K1/116 , H05K1/14 , H05K1/141 , H05K1/162 , H05K1/18 , H05K2201/0939 , H05K2201/09418 , H05K2201/09454 , H05K2201/09463 , H05K2201/09636 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734
Abstract: First and second signal wiring patterns are formed in a first conductor layer. A first electrode pad electrically connected to the first signal wiring pattern through a first via and a second electrode pad electrically connected to the second signal wiring pattern through a second via are formed in a second conductor layer as a surface layer. A third conductor layer is disposed between the first conductor layer and the second conductor layer with an insulator interposed between those conductor layers. A first pad electrically connected to the first via is formed in the third conductor layer. The first pad includes an opposed portion which overlaps the second electrode pad as viewed in a direction perpendicular to the surface of a printed board and which is opposed to the second electrode pad through intermediation of the insulator. This enables reduction of crosstalk noise caused between the signal wirings.
Abstract translation: 第一和第二信号布线图案形成在第一导体层中。 通过第一通孔电连接到第一信号布线图案的第一电极焊盘和通过第二通孔电连接到第二信号布线图案的第二电极焊盘形成在作为表面层的第二导体层中。 第三导体层设置在第一导体层和第二导体层之间，绝缘体插在这些导体层之间。 电连接到第一通孔的第一焊盘形成在第三导体层中。 第一焊盘包括与垂直于印刷电路板的表面的方向观察的与第二电极焊盘重叠并且通过绝缘体与第二电极焊盘相对的相对部分。 这使得能够减少在信号布线之间引起的串扰噪声。
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公开(公告)号：US09113555B2
公开(公告)日：2015-08-18
申请号：US13725556
申请日：2012-12-21
Applicant: Intel Corporation
Inventor： Raul Enriquez Shibayama , Xiaoning Ye , Kai Xiao , Benjamin Lopez Garcia
CPC classification number: H05K1/0228 , H05K1/0245 , H05K1/0251 , H05K1/162 , H05K2201/09636 , Y10T29/49147
Abstract: A method of reducing crosstalk. The method may include forming a first contact over a first vertical conductor. The method may include forming a second contact over a second vertical conductor. The method may include forming a capacitive coupler between the first contact and the second contact, wherein the capacitive coupler is to cancel crosstalk received at the second vertical conductor from the first vertical conductor.
Abstract translation: 减少串扰的方法。 该方法可以包括在第一垂直导体上形成第一接触。 该方法可以包括在第二垂直导体上形成第二接触。 该方法可以包括在第一触点和第二触点之间形成电容耦合器，其中电容耦合器将消除来自第一垂直导体的在第二垂直导体处接收的串扰。
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公开(公告)号：US09084353B2
公开(公告)日：2015-07-14
申请号：US13807325
申请日：2011-06-28
Applicant: Jan De Geest , Stefaan Hendrik Jozef Sercu
Inventor： Jan De Geest , Stefaan Hendrik Jozef Sercu
CPC classification number: H05K1/0251 , H05K1/024 , H05K1/0245 , H05K1/115 , H05K3/429 , H05K2201/0187 , H05K2201/09063 , H05K2201/09618 , H05K2201/09636 , H05K2201/09718 , H05K2201/10189
Abstract: A circuit board (1) is provided comprising a plurality of insulating layers, at least one ground layer and at least one layer comprising signal traces. The circuit board comprises at least a first conductive via (17) and a second conductive via (17). The first conductive via and the second conductive via penetrate through at least a first insulating layer of the plurality of insulating layers and are connected to a signal trace. The first conductive via and the second conductive via are arranged adjacent each other. At least in the first insulating layer the first conductive via and the second conductive via are separated in a first direction of separation (R) by a first adjustment portion comprising a dielectric material property different from the first insulating layer.
Abstract translation: 提供电路板（1），其包括多个绝缘层，至少一个接地层和至少一个包含信号迹线的层。 电路板包括至少第一导电通孔（17）和第二导电通孔（17）。 第一导电通孔和第二导电通孔穿透多个绝缘层中的至少第一绝缘层，并连接到信号迹线。 第一导电通孔和第二导电通孔彼此相邻布置。 至少在第一绝缘层中，通过包括不同于第一绝缘层的介电材料性质的第一调节部分，第一导电通孔和第二导电通孔在第一分离方向（R）分离。
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公开(公告)号：US20130199834A1
公开(公告)日：2013-08-08
申请号：US13807325
申请日：2011-06-28
Applicant: Jan De Geest , Stefaan Hendrik Jozef Sercu
Inventor： Jan De Geest , Stefaan Hendrik Jozef Sercu
IPC: H05K1/11
CPC classification number: H05K1/0251 , H05K1/024 , H05K1/0245 , H05K1/115 , H05K3/429 , H05K2201/0187 , H05K2201/09063 , H05K2201/09618 , H05K2201/09636 , H05K2201/09718 , H05K2201/10189
Abstract: A circuit board (1) is provided comprising a plurality of insulating layers, at least one ground layer and at least one layer comprising signal traces. The circuit board comprises at least a first conductive via (17) and a second conductive via (17). The first conductive via and the second conductive via penetrate through at least a first insulating layer of the plurality of insulating layers and are connected to a signal trace. The first conductive via and the second conductive via are arranged adjacent each other. At least in the first insulating layer the first conductive via and the second conductive via are separated in a first direction of separation (R) by a first adjustment portion comprising a dielectric material property different from the first insulating layer.
Abstract translation: 提供电路板（1），其包括多个绝缘层，至少一个接地层和至少一个包含信号迹线的层。 电路板包括至少第一导电通孔（17）和第二导电通孔（17）。 第一导电通孔和第二导电通孔穿透多个绝缘层中的至少第一绝缘层，并连接到信号迹线。 第一导电通孔和第二导电通孔彼此相邻布置。 至少在第一绝缘层中，通过包括不同于第一绝缘层的介电材料性质的第一调节部分，第一导电通孔和第二导电通孔在第一分离方向（R）分离。
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Patent Agency Ranking
166.发明授权Structure of multiple coaxial leads within single via in substrate and manufacturing method thereof 有权单个通孔中多个同轴引线在基片中的结构及其制造方法公开(公告)号：US08304666B2
公开(公告)日：2012-11-06
申请号：US12468058
申请日：2009-05-19
Applicant: Cheng-Ta Ko , Min-Lin Lee , Wei-Chung Lo , Shur-Fen Liu , Jinn-Shing King , Shinn-Juh Lai , Yu-Hua Chen
Inventor： Cheng-Ta Ko , Min-Lin Lee , Wei-Chung Lo , Shur-Fen Liu , Jinn-Shing King , Shinn-Juh Lai , Yu-Hua Chen
IPC: H05K1/11
CPC classification number: H05K1/0222 , H05K3/429 , H05K2201/09636 , H05K2201/09645 , H05K2201/09809
Abstract: A plurality of coaxial leads is made within a single via in a circuit substrate to enhance the density of vertical interconnection so as to match the demand for higher density multi-layers circuit interconnection between top circuit layer and bottom circuit layer of the substrate. Coaxial leads provide electromagnetic interference shielding among the plurality of coaxial leads in a single via.
Abstract translation: 多个同轴引线在电路基板中的单个通孔内形成，以增强垂直互连的密度，以便匹配在衬底的顶层电路层和底层电路层之间的较高密度多层电路互连的需求。 同轴引线在单个通孔中提供多个同轴引线之间的电磁干扰屏蔽。
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公开(公告)号：US20120039010A1
公开(公告)日：2012-02-16
申请号：US12856276
申请日：2010-08-13
Applicant: Andrew F. Tresness
Inventor： Andrew F. Tresness
IPC: H02H7/20
CPC classification number: H05K1/026 , H01T4/08 , H05K1/116 , H05K3/0038 , H05K2201/09036 , H05K2201/09636 , H05K2203/0242
Abstract: A spark gap for protecting electronic circuits from excessive electrical surges comprises a substrate containing an opening, a dielectric medium occupying the opening, and first and second electrodes. The first electrode is embedded in the substrate, on one side of the opening, and has a first conductive surface that extends through the substrate and is substantially exposed in the opening and to the dielectric medium. The second electrode is embedded in the substrate, on another side of the opening, and has a second conductive surface that extends through the substrate and is substantially exposed in the opening and to the dielectric medium. The first conductive surface is in opposing relation to the second conductive surface, and they are spaced apart by a predetermined distance to establish a gap width. An electrical arc is generated across the opening when a voltage potential difference between the conductive surfaces exceeds a threshold value.
Abstract translation: 用于保护电子电路不受过度电涌影响的火花隙包括含有开口的基板，占据开口的电介质以及第一和第二电极。 第一电极在开口的一侧嵌入衬底中，并且具有延伸穿过衬底并基本上暴露在开口和电介质中的第一导电表面。 第二电极嵌入基板中，在开口的另一侧上，并且具有延伸穿过基板的第二导电表面，并且基本上暴露在开口和介电介质中。 第一导电表面与第二导电表面相对，并且它们间隔开预定距离以建立间隙宽度。 当导电表面之间的电压差超过阈值时，跨越开口产生电弧。
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公开(公告)号：US20120031654A1
公开(公告)日：2012-02-09
申请号：US13278199
申请日：2011-10-21
Applicant: Wei-Ting Chen , Chang-Sheng Chen , Chin-Sun Shyu , Chang-Lin Wei , Cheng-Hua Tsai , Kuo-Chiang Chin
Inventor： Wei-Ting Chen , Chang-Sheng Chen , Chin-Sun Shyu , Chang-Lin Wei , Cheng-Hua Tsai , Kuo-Chiang Chin
CPC classification number: H05K1/162 , H01G4/012 , H01G4/228 , H01G4/33 , H01L23/50 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0237 , H05K1/115 , H05K2201/09309 , H05K2201/09636 , H05K2201/0969 , H05K2201/09718 , H01L2924/00
Abstract: A dual-port capacitor structure includes a first electrode plate having a first opening; a second electrode plate having a second opening; and a third electrode plate, disposed in the first opening of the first electrode plate and the second opening of the second electrode plate. The first electrode plate, the second electrode plate and the third electrode plate locate on the same plane.
Abstract translation: 双端口电容器结构包括具有第一开口的第一电极板; 具有第二开口的第二电极板; 以及第三电极板，设置在第一电极板的第一开口和第二电极板的第二开口中。 第一电极板，第二电极板和第三电极板位于同一平面上。
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169.发明申请ADJACENT PLATED THROUGH HOLES WITH STAGGERED COUPLINGS FOR CROSSTALK REDUCTION IN HIGH SPEED PRINTED CIRCUIT BOARDS 失效在高速印刷电路板中用于降低CROSSTALK的STAGGERED耦合的通孔公开(公告)号：US20120000701A1
公开(公告)日：2012-01-05
申请号：US13187173
申请日：2011-07-20
Applicant: Jason Edward CHAN , Jose Ricardo Paniagua
Inventor： Jason Edward CHAN , Jose Ricardo Paniagua
IPC: H05K1/11
CPC classification number: H01R12/523 , H01R12/58 , H01R13/6461 , H01R13/6477 , H05K1/0216 , H05K1/0245 , H05K1/0298 , H05K3/429 , H05K2201/09236 , H05K2201/09636 , H05K2201/09845 , H05K2203/0242
Abstract: An electrical signal connection, an electrical signaling system, and a method of connecting printed circuit boards. The electrical signal connection having a first conductive via and a second conductive via disposed in a first printed circuit board. A first conductive trace with a first end and a second end has the first end electrically coupled to the first conductive via at a first distance from the top surface of the first printed circuit board. The second end of the first conductive via is electrically coupled to the second printed circuit board. A second conductive trace with a first end and a second end has the first end being electrically coupled to the second conductive via at a second distance from the top surface of the first printed circuit board. The second end being is electrically coupled to the second printed circuit board.
Abstract translation: 电信号连接，电信号系统和连接印刷电路板的方法。 电信号连接具有设置在第一印刷电路板中的第一导电通孔和第二导电通孔。 具有第一端和第二端的第一导电迹线具有与第一印刷电路板的顶表面第一距离处电耦合到第一导电通孔的第一端。 第一导电通孔的第二端电耦合到第二印刷电路板。 具有第一端和第二端的第二导电迹线具有第一端部，其与第一印刷电路板的顶表面距离第二距离电耦合到第二导电通孔。 第二端电连接到第二印刷电路板。
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公开(公告)号：US08077443B2
公开(公告)日：2011-12-13
申请号：US12109356
申请日：2008-04-25
Applicant: Wei-Ting Chen , Chang-Sheng Chen , Chin-Sun Shyu , Chang-Lin Wei , Cheng-Hua Tsai , Kuo-Chiang Chin
Inventor： Wei-Ting Chen , Chang-Sheng Chen , Chin-Sun Shyu , Chang-Lin Wei , Cheng-Hua Tsai , Kuo-Chiang Chin
CPC classification number: H05K1/162 , H01G4/012 , H01G4/228 , H01G4/33 , H01L23/50 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0237 , H05K1/115 , H05K2201/09309 , H05K2201/09636 , H05K2201/0969 , H05K2201/09718 , H01L2924/00
Abstract: A capacitor structure is provided. In the capacitor structure, a signal electrode plate and an extension ground electrode plate are disposed on the same plane to form a co-plane capacitor structure. Due to slow wave characteristic, the resonance frequency of the capacitor structure is effectively raised and the capacitor structure may be applied in high frequency.
Abstract translation: 提供电容器结构。 在电容器结构中，信号电极板和延伸接地电极板设置在同一平面上以形成共面电容器结构。 由于慢波特性，电容器结构的谐振频率有效提高，电容器结构可以高频应用。
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