公开(公告)号：ITMI911390D0

公开(公告)日：1991-05-21

申请号：ITMI911390

申请日：1991-05-21

Applicant: CONS RIC MICROELETTRONICA

Inventor： SUERI STEFANO ,  PALARA SERGIO

IPC: H03K17/042 ,  H03K17/14 ,  H03K17/64 ,  G05F

Abstract: The driving circuit comprises a detection resistance (R1) interposed between the emitter of the power transistor (T1) and ground, a first circuit part (G1, T4, T5, R2) suitable for generating a first current (I2) being a function of the voltage across said detection resistance (R1) and a second circuit part (TD2, T3, TD1, T2) suitable for generating a driving base current (Ib) of the power transistor (T1) that is proportional to said first current (I2).

公开(公告)号：ITMI911266D0

公开(公告)日：1991-05-09

申请号：ITMI911266

申请日：1991-05-09

Applicant: CONS RIC MICROELETTRONICA

Inventor： PALARA SERGIO ,  SUERI STEFANO

IPC: H02H7/00 ,  F02P3/04 ,  H02H7/12 ,  H03K3/286 ,  H03K17/082 ,  H01L

公开(公告)号：ITMI910836D0

公开(公告)日：1991-03-28

申请号：ITMI910836

申请日：1991-03-28

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/22 ,  H01L29/73 ,  H01L21/322 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861 ,  H01L

Abstract: The structure consists of a single chip (1) of semiconductor material, which comprises an area (32) having a high lifetime of the minority carriers, which constitutes a bipolar power device with high current density, and at least one area (20, 21; 20', 21') with a reduced lifetime of the minority carriers, which constitutes a fast diode.

公开(公告)号：IT9022113D0

公开(公告)日：1990-11-20

申请号：IT2211390

申请日：1990-11-20

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAPISARDA CIRINO

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76 ,  H01L21/762 ,  H01L

公开(公告)号：IT9006609D0

公开(公告)日：1990-04-20

申请号：IT660990

申请日：1990-04-20

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/78 ,  H01L

Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage in comparison with known structures by provision of one or more regions of high dopant concentration defined after growth of a first epitaxial layer.

公开(公告)号：DE69434937D1

公开(公告)日：2007-04-19

申请号：DE69434937

申请日：1994-06-23

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: A zero thermal budget process for the manufacturing of a MOS-technology vertical power device (such as a MOSFET or a IGBT) comprises the steps of: forming a conductive Insulated gate layer (8) on a surface of a lightly doped semiconductor material layer (3) of a first conductivity type; selectively removing the insulated gate layer (8) from selected portions of the semiconductor material layer (3) surface; selectively implanting a first dopant of a second conductivity type into said selected portions of the semiconductor material layer (3), the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, heavily doped regions (5) substantially aligned with the edges of the insulated gate layer (8); selectively implanting a second dopant of the second conductivity type along directions tilted of prescribed angles ( alpha 1, alpha 2) with respect to a direction orthogonal to the semiconductor material layer (3) surface, the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, lightly doped channel regions (6) extending under the insulated gate layer (8); selectively implanting a heavy dose of a third dopant of a first conductivity type into the heavily doped regions (5), to form source regions (7) substantially aligned with the edges of the insulated gate layer (8).

公开(公告)号：DE69533308T2

公开(公告)日：2004-11-25

申请号：DE69533308

申请日：1995-05-16

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： PULVIRENTI FRANCESCO ,  GARIBOLDI ROBERTO

IPC: G01R19/165 ,  G01R31/02 ,  G05B19/042 ,  G05B19/05

Abstract: The invention relates to a method for detecting an open load by means of a driver having at least one main power transistor (M10) connected to the load (L) and one auxiliary transistor (M11) connected in parallel with the main transistor (M10) between a first power supply voltage reference (Vs) and a second voltage reference (GND), the method providing a comparison between a first voltage (VIN1) present on a terminal (S10) connected to the load of the main transistor (M10) and a second voltage (VIN2) present on a terminal (S11) of the auxiliary transistor (M11). The invention also relates to a circuit for detecting an open load (L), in which the said method is implemented.

公开(公告)号：DE69434039D1

公开(公告)日：2004-11-04

申请号：DE69434039

申请日：1994-12-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO ,  GNUDI ANTONIO

IPC: G05F3/24 ,  G05F3/26

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises: a) at least two transistors (M1, M2) of the same type having respectively two control terminals (G1, G2) and having essentially the same threshold with each of said two transistors (M1, M2) also having a first (S1, S2) and a second (D1, D2) main conduction terminal, b) a current mirror (MC) having at least two input-output terminals (IM, OM) with said two terminals (IM, OM) coupled respectively to said two transistors (M1, M2) so as to supply to them the bias currents, c) a voltage generator (VG) connected between said two control terminals (G1, G2), and d) a feedback path (FP) between said control terminals (G1, G2) and one (OM) of said input-output terminals. The output (OT) is coupled to one (G2) of said control terminals.

公开(公告)号：DE69233154D1

公开(公告)日：2003-09-18

申请号：DE69233154

申请日：1992-11-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/772

公开(公告)号：DE69530077D1

公开(公告)日：2003-04-30

申请号：DE69530077

申请日：1995-07-31

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： PALARA SERGIO ,  GRAZIANO VITO

IPC: H02M7/5383 ,  H03K17/16 ,  H03K17/284 ,  H05B41/282 ,  H05B41/00 ,  H03K17/687 ,  H05B41/295

Abstract: The principle on which the start up circuit of this invention operates is that of causing the MOS transistor (M2) to be turned on by sensing local electrical quantities thereof, specifically the potential at the drain terminal (D) of the MOS transistor (M2). The basic idea is to inject a small current into the control terminal (G) when the potential at the drain terminal (D) is high. For the purpose, an electric network (SN) is arranged to couple these two terminals together.