公开(公告)号：EP1672791A2

公开(公告)日：2006-06-21

申请号：EP05112285.1

申请日：2005-12-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Tiwari, Naveen ,  Singh, Balwant

IPC: H03K3/03

CPC classification number: G06F1/04 ,  H03K3/0315 ,  H03K3/70

Abstract: A glitch free controlled ring oscillator comprising a programmable delay chain connected to a gating and inverting means wherein a latching means is provided between said delay chain and said gating and inverting means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to said registered clock state.

Abstract translation: 一种无毛刺控制环形振荡器，包括连接到门控和反相装置（3）的可编程延迟链（1），其中在所述可编程延迟链（1）和所述选通和反相装置（3）之间提供锁存装置（2） 用于在禁止振荡器并将振荡器的输出设置为所述注册的时钟状态时注册时钟状态。

公开(公告)号：EP1653331A2

公开(公告)日：2006-05-03

申请号：EP05110131.9

申请日：2005-10-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： DHIMAN, Gaurav ,  KAPOOR, Gaurav

IPC: G06F1/20 ,  G06F1/32

CPC classification number: G06F1/30 ,  G06F1/3203 ,  G06F9/4418

Abstract: An apparatus for entering and exiting low power mode comprising a processor having a cache; a power management mechanism connected to said processor for controlling a plurality of power management states, at least one of said power management states being a low latency low power state; a memory subsystem including a self sustaining mechanism connected to said processor for retaining data during said low power state; a prefetching means in said memory subsystem for loading instructions into a cache prior to entering said low power state; a disabling mechanism in said processor for disabling any interrupts that may disturb said prefetched instructions; an enabling means in said memory subsystem for initiating the self sustaining operation of said memory subsystem; a detecting means connected to said processor for sensing a trigger to exit from said low power state; and a restoring means in said power management mechanism for restoring the clock of said apparatus; thereby said processor disabling said self sustaining operation and resuming normal operation at the end of said low power state.

Abstract translation: 对于进入和退出低功率模式，其包括具有高速缓存的处理器的装置; 连接到所述处理器，用于控制电源管理状态，所述电源管理状态是低等待时间低功率状态中的至少一个的多个电源管理机制; 存储器子系统包括连接到所述处理器，用于所述低功率状态期间保持的数据的自我维持机构; 预取在用于加载指令到高速缓存所述存储器子系统进入所述低功率状态之前，装置; 一个禁用在所述处理器机制，用于禁止任何中断都可能干扰。所述预取指令; 在所述存储器子系统使能装置，用于启动自维持存储器子系统的操作。所述; 检测连接到所述处理器，用于感测触发从所述低功率状态退出的装置; 和恢复在所述电源管理机制用于恢复所述设备的时钟; 由此，所述处理器禁用所述自持运行，并在所述低功率状态的结束恢复正常运作。

公开(公告)号：EP1447752A3

公开(公告)日：2006-02-22

申请号：EP04100617.2

申请日：2004-02-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Narayan, Srijib

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: The present invention provides a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements, comprising computing each butterfly of the first "log 2 P" stages on either a single processor or each of the "P" processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the "P" processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
The invention also provides a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements.

公开(公告)号：EP1603239A1

公开(公告)日：2005-12-07

申请号：EP05011771.2

申请日：2005-06-01

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Nitin

IPC: H03K19/003

CPC classification number: H03K19/00315

Abstract: An voltage tolerant protection circuit for input buffer comprising a transmission gate circuit (11) receiving input from a pad for passing the input signal to the input of the input buffer, a control signal generator (12) connected between said transmission gate circuit (11) and the pad to provide a control signal (PMOSCTRL) for operating said transmission gate circuit (11), and an N-Well generation circuit (13) connected between the pad and said transmission gate circuit (11), and also connected to said control signal generator (12) for generating a bias signal (NWELL) for said transmission gate circuit (11) and said control signal generator (12). Thus, the present invention provides a voltage tolerant protection circuit that prevents electrical stress on transistors comprised within the transmission gate circuit (11) and the control signal generator (12), minimizes power supply consumption and transfers signals without any change in amplitude.

Abstract translation: 一种用于输入缓冲器的耐压保护电路，包括：传输门电路（11），接收来自焊盘的输入，用于将输入信号传递到输入缓冲器的输入;控制信号发生器（12），连接在所述传输门电路（11） 以及提供用于操作所述传输门电路（11）的控制信号（PMOSCTRL）的焊盘和连接在焊盘和所述传输门电路（11）之间的N阱产生电路（13），并且还连接到所述控制 信号发生器（12），用于产生用于所述传输门电路（11）和所述控制信号发生器（12）的偏置信号（NWELL）。 因此，本发明提供了一种耐电压保护电路，其防止在传输门电路（11）和控制信号发生器（12）内的晶体管的电应力，使电源消耗最小化并传输信号而没有任何幅度变化。

公开(公告)号：EP1585139A1

公开(公告)日：2005-10-12

申请号：EP05102753.0

申请日：2005-04-07

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Bahl, Swapnil ,  Singh, Balwant

IPC: G11C29/00 ,  G01R31/317 ,  G01R31/3187

CPC classification number: G11C29/16 ,  G01R31/31724 ,  G11C29/006 ,  G11C29/12015 ,  G11C2029/1208 ,  G11C2029/5602

Abstract: An on-chip and at-speed testerfor testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localised Signal Generators located inside each memory block and controlled by said Centralized Flow Controlle for applying specified test patterns on the associated memory array.

Abstract translation: 一种用于在集成电路器件中测试和表征不同类型存储器的片上和速度测试器，其包括用于自动控制所选测试程序的测试操作的集中流量控制器和位于每个存储器块内的本地化信号发生器，并被控制 通过所述集中流控制器在相关联的存储器阵列上应用指定的测试图案。

公开(公告)号：EP1510950A3

公开(公告)日：2005-09-21

申请号：EP04104132.8

申请日：2004-08-27

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Sharma, Sunil Kumar ,  Tomar, Ajay ,  Samanta, Dhabalendu

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: An improved method for finding a maximum volume minimum cutset in a network of interconnected nodes, applicable to any system that can be reduced to such network including telecommunication network, traffic network, computer networks, layouts, hydraulic networks etc. According to the invention an equivalent network is derived by replacing all nodes other then source and sink by two interconnected nodes, a conventional method applying augmenting path algorithm identifies then a cutset. If the feasible cutset is not achieved than a reduced network is constructed by directly connecting the member nodes of identified cutset to the source node and repeating the above process for the reduce network until a feasible cutset is achieved.

公开(公告)号：EP1517335A2

公开(公告)日：2005-03-23

申请号：EP04018572.0

申请日：2004-08-05

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Ahmad, Nasim

IPC: G11C29/00

CPC classification number: G11C29/804 ,  G11C11/41 ,  G11C29/806

Abstract: The present invention relates to an improved semiconductor memory device providing row/column redundancy comprising a plurality of data latches (11) arranged in a row-column matrix connected to a set of bitlines / global bitlines interfacing to read/write circuitry, at least two redundant rows/columns (R1, R2) connected to a redundant bitline / global bitline, a first means (5) for providing a first faulty row/column address in the matrix, a second means (1, 16) for generating other faulty row/column addresses by incrementing or decrementing predetermined numbers from the address provided by the first means (5), a comparison circuitry (3, 13) receiving as its inputs the accessed row/column address and the faulty row/column addresses and a control block (4, 14) connected to the comparison circuitry (3, 13) and receiving a control signal (REN, CS) for normal operation of the memory device, the control block (4, 14) enabling/disabling the redundant rows/columns (R1, R2) and/or other memory cell rows/columns depending upon signals received from the comparison circuitry (3, 13) and the control signal (CS) for normal operation of the memory device.

Abstract translation: 本发明涉及一种提供行/列冗余的改进的半导体存储器件，其包括多个数据锁存器（11），所述数据锁存器（11）布置成与连接到读/写电路的一组位线/全局位线连接的行 - 列矩阵，至少两个 连接到冗余位线/全局位线的冗余行/列（R1，R2），用于在矩阵中提供第一故障行/列地址的第一装置（5），用于产生其他故障行的第二装置（1,16） /列地址，通过从由第一装置（5）提供的地址中增加或减少预定数量;比较电路（3,13），其接收访问的行/列地址和有故障的行/列地址作为其输入;以及控制块 （4,14），连接到比较电路（3,13）并且接收用于存储器装置的正常操作的控制信号（REN，CS），所述控制块（4,14）启用/禁用冗余行/列（ R1，R2）和/或其他记忆 y单元行/列，这取决于从比较电路（3,13）接收的信号和用于存储器件正常操作的控制信号（CS）。

公开(公告)号：EP1510950A2

公开(公告)日：2005-03-02

申请号：EP04104132.8

申请日：2004-08-27

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Sharma, Sunil Kumar ,  Tomar, Ajay ,  Samanta, Dhabalendu

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: An improved method for finding a maximum volume minimum cutset in a network of interconnected nodes, applicable to any system that can be reduced to such network including telecommunication network, traffic network, computer networks, layouts, hydraulic networks etc. According to the invention an equivalent network is derived by replacing all nodes other then source and sink by two interconnected nodes, a conventional method applying augmenting path algorithm identifies then a cutset. If the feasible cutset is not achieved than a reduced network is constructed by directly connecting the member nodes of identified cutset to the source node and repeating the above process for the reduce network until a feasible cutset is achieved.

Abstract translation: 为互连节点的网络中找到的最大体积最小割集的改进的方法，可适用于任何系统也可以减少到寻求网络包括电信网络，交通网络，计算机网络，布局，液压网络等。据的等效发明 网络是由两个相互连接的节点替换其他所有节点然后源和宿衍生，应用增强路径算法的常规方法随后识别一个割集。 如果可行割集不大于减小的网络实现，是由鉴定割集的成员节点直接连接到源节点并重复上述处理，直到一个可行的割集实现所述减少网络构成。

公开(公告)号：EP1505732A1

公开(公告)日：2005-02-09

申请号：EP04103610.4

申请日：2004-07-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： NANDY, Tapas

IPC: H03K7/06 ,  H03K7/04

CPC classification number: H03K5/133 ,  H03K5/1252 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/067

Abstract: The present invention provides a digital clock modulator providing a smoothly modulated clock period to reduce emitted Electro-Magnetic Radiation (EMR) comprising a plurality of delay elements (14) connected in series receiving an unmodulated clock signal at the input, connected to a multiplexer (11) receiving inputs from unequally spaced selected taps provided between the delay elements. A control block (12) supplies the selection-inputs to said multiplexer (11), and receives a clock signal from said series of delay elements. Further, a predetermined delay element (13) is connected between the clock terminal of the said control block (12) and the last element U(n) of said series of delay elements for enabling glitch free operation by ensuring that the entire delay chain and related signal paths are in the same stable state before the control to the multiplexer changes.

Abstract translation: 本发明提供了一种数字时钟调制器，其提供平滑调制的时钟周期以减少发射的电磁辐射（EMR），其包括多个延迟元件（14），所述多个延迟元件（14）串联接收连接到多路复用器的输入处的未调制时钟信号 11）从延迟元件之间提供的不等间隔的选择的抽头接收输入。 控制块（12）将选择输入提供给所述多路复用器（11），并且从所述一系列延迟元件接收时钟信号。 此外，预定的延迟元件（13）连接在所述控制块（12）的时钟端子和所述一系列延迟元件的最后一个元件U（n）之间，以便通过确保整个延迟链和 在对多路复用器的控制变化之前，相关的信号路径处于相同的稳定状态。

公开(公告)号：EP1411431A2

公开(公告)日：2004-04-21

申请号：EP03020154.5

申请日：2003-09-05

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Goel, Ashish Kumar ,  Khanna, Namerita ,  Aggarwal, Davinder

IPC: G06F11/14

CPC classification number: G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

Abstract: The invention provides an improved method and apparatus for reloading only those frames in which errors are detected during the FPGA configuration. A configuration data frame for a FPGA is sumultaneously loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value 'n'. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and recheked for errors. If no error os detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

Abstract translation: 一个新的配置数据帧被加载到帧寄存器和误差检测电路（700）。 在数据帧中的错误进行检查，并且如果没有检测到错误的数据的可编程逻辑器件存储器锁存器的传输被执行。 帧寄存器重新加载和错误计数器（706）的值被递增，如果遇到错误。 因此独立claimsoft包含用于可编程逻辑器件。