公开(公告)号：EP1965480A2

公开(公告)日：2008-09-03

申请号：EP08152094.2

申请日：2008-02-28

Applicant: STMicroelectronics, Inc.

Inventor： Burlask, Gary Joseph ,  Marowski, Marian

IPC: H02H3/12 ,  H02J9/00

CPC classification number: H02H3/12 ,  Y10T307/549

Abstract: A method and integrated circuit for preserving a battery's charge and protecting electrical devices is disclosed. A maximum and a minimum battery voltage value at the output port are stored in a memory. A steady state battery voltage at the output port is measured and stored in the memory. A processor compares the measured steady battery voltage value to the maximum and the minimum battery voltage values. If the measured steady state battery voltage value is greater than the maximum battery voltage value, an over voltage state is reported by the processor, If the measured steady state battery voltage value is less than the minimum battery voltage value, a low battery voltage state is reported by the processor.

Abstract translation: 一种用于保存一个电池的充电和保护电气设备的方法和集成电路是游离缺失盘。 最大，并在输出端口的最小电池电压值被存储在存储器中。 在输出端口处稳态电池电压被测量并存储在存储器中。 处理器将测量的稳定的电池电压值的最大值和最小值的电池电压值。 如果比在过压状态下的最大的电池电压值由处理器报告，如果测得的稳态电池电压值是小于最小电池电压值的测量稳定状态的电池电压值越大，低电池电压状态是 由所述处理器的报道。

公开(公告)号：EP1484711A3

公开(公告)日：2008-09-03

申请号：EP04253068.3

申请日：2004-05-25

Applicant: STMicroelectronics, Inc.

Inventor： Leaming, Taylor J.

IPC: G06K19/07

CPC classification number: G06K19/06206 ,  G06K19/07

Abstract: An emulator for a smart card device and associated method have at least two virtual components as functional blocks for a smart card device and operative in different clock domains. A functional buffering block is operative for communicating with the functional blocks and buffering between the functional blocks and allowing emulation.

公开(公告)号：EP1962290A1

公开(公告)日：2008-08-27

申请号：EP08151480.4

申请日：2008-02-15

Applicant: STMicroelectronics, Inc.

Inventor： Lysinger, Mark A. ,  McClure, David C. ,  Jacquet, François

IPC: G11C11/413 ,  G11C11/417 ,  G11C5/14

CPC classification number: G11C5/143 ,  G11C11/412 ,  G11C11/413

Abstract: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can comprise a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.

Abstract translation: 电路包括具有高电压供应节点和低电压供应节点的存储单元。 提供功率复用电路以根据小区的当前操作模式来选择性地将第一组电压和第二组电压中的一个施加到小区的高电压和低电压供应节点。 如果单元处于活动读或写模式，则多路复用电路选择性地将第一组电压施加到高电压和低电压供应节点。 相反，如果单元处于待机无读或不写模式，则多路复用电路选择性地将第二组电压施加到高电压和低电压供应节点。 第二组电压偏离第一组电压。 更具体地，第二组电压中的低电压高于第一组电压中的低电压，并且其中第二组电压中的高电压小于第一组电压中的高电压。 单元可以是单元阵列的成员，在这种情况下，根据阵列的主动/待机模式，选择性地施加电压应用于阵列。 该阵列可以包括包括许多块或部分的整个存储器装置内的块或部分，在这种情况下，根据块/部分本身的主动/待机模式，选择性地施加电压施加到各个块/部分。

公开(公告)号：EP1944996A2

公开(公告)日：2008-07-16

申请号：EP08150130.6

申请日：2008-01-09

Applicant: STMicroelectronics, Inc

Inventor： Hu, Wendong

IPC: H04Q7/38

CPC classification number: H04W72/085 ,  H04W16/14 ,  H04W72/082

Abstract: In order to satisfy the conflicting requirements for spectrum sensing and QoS of data transmission, it is highly desirable for a cognitive radio system, e.g. IEEE 802.22 WRAN, to perform spectrum sensing and data transmission simultaneously. Embodiments of the invention address critical issues of self-interference generated from a transmission unit to the co-located sensing unit when the simultaneous sensing and data transmission technique is applied. A number of interference mitigation techniques are described and analyses are given.

Abstract translation: 为了满足数据传输的频谱感测和QoS的冲突要求，非常希望认知无线电系统，例如， IEEE 802.22 WRAN，同时进行频谱感测和数据传输。 当应用同时感测和数据传输技术时，本发明的实施例解决了从传输单元到共处感测单元产生的自干扰的关键问题。 描述了许多干扰减轻技术，并给出了分析。

公开(公告)号：EP1462944A3

公开(公告)日：2008-05-28

申请号：EP04251765.6

申请日：2004-03-26

Applicant: STMicroelectronics, Inc.

Inventor： Longo, Alan ,  Catalano, Glen ,  Lammers, Brett ,  Lott, Glenn Alan ,  Tempero, William Morgan ,  Wilson, Aaron Wade

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0871 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0676 ,  G06F2212/312 ,  G06F2212/462

Abstract: An extent record for an extent based data buffer that includes a host pointer that links the extent record to a next host extent record of a host extent record set, and a storage device pointer that links the extent record to a next storage device extent record of a storage device extent record set. Also, a system for transferring data between a host and a storage device that includes a data buffer coupled to the host and the storage device, where memory in the data buffer is divided into one or more extents, an extent table associated with the data buffer, where the extent table includes at least one extent record, an LBA chain table coupled to the host and the extent table, and a track section table coupled to the storage device and the extent table.

公开(公告)号：EP1355273A3

公开(公告)日：2008-01-16

申请号：EP03252412.6

申请日：2003-04-16

Applicant: STMicroelectronics, Inc.

Inventor： NG, Kim Chai

IPC: G06T7/00

CPC classification number: G06K9/20 ,  G06K2209/40 ,  G06T7/55

Abstract: An image processing system and method for smoothing irregularities from 3D image information that was reconstructed from a plurality of 2D views of a scene, and particularly from homogeneous surfaces of objects in a scene. The method defines a window that overlaps a plurality of pixels of one of a plurality of 2D image views of a scene. Each pixel is associated with predefined 3D depth information, and further is associated with a matching curve. A subject pixel is located within the plurality of pixels overlapped by the window. The method calculates an average 3D depth information associated with the plurality of pixels overlapped by the window, and assigns the calculated average 3D depth information to the 3D depth information of the subject pixel, if the calculated average 3D depth information is within an error region of a matching curve associated with the subject pixel.

公开(公告)号：EP1860062A2

公开(公告)日：2007-11-28

申请号：EP07252093.5

申请日：2007-05-22

Applicant: STMicroelectronics, Inc.

Inventor： Bryant, Frank ,  Robinson, Murray

IPC: B81C1/00

CPC classification number: B81C1/00119 ,  B81B2203/0315 ,  B81C2201/0109

Abstract: A microfabricated structure and method of making that includes forming a first layer of material on a substrate, forming patterned sacrificial material having a predetermined shape on the first layer of material, and forming a second layer of material over the first layer and the patterned sacrificial material, which is then removed to form an encapsulated cavity. Ideally, the first and second layers are formed of the same type material. A structural support layer can be added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

Abstract translation: 微制造结构及其制造方法包括在基板上形成第一层材料，在第一层材料上形成具有预定形状的图案化牺牲材料，以及在第一层上形成第二层材料，并将图案化的牺牲材料 ，然后将其除去以形成封装腔体。 理想地，第一层和第二层由相同类型的材料形成。 结构支撑层可以添加到第二层。 可以在空腔中形成开口，并且空腔可以并排层叠，通过开口垂直地堆叠有互连，并且两者的组合可以用于构造整个具有互连的堆叠阵列。

公开(公告)号：EP1710693A3

公开(公告)日：2007-11-14

申请号：EP06251747.9

申请日：2006-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Rizzo, Davide

IPC: G06F9/38

CPC classification number: G06F9/383

Abstract: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is.transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.

公开(公告)号：EP1383033A3

公开(公告)日：2007-11-14

申请号：EP03253400.0

申请日：2003-05-30

Applicant: STMicroelectronics, Inc.

Inventor： Wenzel, Edward

IPC: G06F1/32 ,  G05F1/571

CPC classification number: G06F1/28 ,  G05F1/569 ,  G06F1/26 ,  Y10T307/944

Abstract: A power limiting circuit for power supply that is controlled by a power supply control module includes a shunt regulator having a reference input operatively connected to a voltage input that receives a voltage representative of the power supply control module connected thereto. The shunt regulator is biased on when the voltage at the reference input increases above a reference voltage established at the voltage input. A transistor is operatively connected to the shunt regulator and to an output operatively connected to the power supply control module and has a voltage that is representative of voltage operating the power supply control module. The transistor is biased on from the shunt regulator such that the shunt regulator and transistor form a latch when the voltage at the output reduces below an off voltage level to turn off the power supply, dropping the input voltage, and restarting the power supply in a restart cycle.

公开(公告)号：EP1848169A1

公开(公告)日：2007-10-24

申请号：EP07075540.0

申请日：2003-05-21

Applicant: STMicroelectronics, Inc.

Inventor： Makarov, Aleksej

IPC: H04L27/233 ,  H04B7/26

CPC classification number: H04L27/2332 ,  H04L27/2275 ,  H04L2027/0065 ,  H04L2027/0087

Abstract: Counter-clockwise and clockwise quadrant transitions are detected and accumulated with respect to a received complex signal over a certain time period. These transitions may then be compared in order to obtain information indicative of both a magnitude and phase of a frequency offset error. Additionally, zero-crossings of the received complex signal over the same certain time period are detected and accumulated. The accumulated crossings provide information indicative of frequency offset magnitude. The determined magnitude and phase of the frequency offset error may then be used to adjust a local oscillator frequency to provide for improved receiver performance.

Abstract translation: 在一段时间内相对于接收到的复合信号检测和累积逆时针和顺时针象限转换。 然后可以比较这些转变以便获得指示频率偏移误差的幅度和相位的信息。 此外，检测并累积在相同的特定时间段内接收的复信号的零交叉。 累积的交叉点提供指示频率偏移幅度的信息。 然后，频率偏移误差的确定幅度和相位可用于调整本地振荡器频率以提供改进的接收机性能。