公开(公告)号：US20170341931A1

公开(公告)日：2017-11-30

申请号：US15650953

申请日：2017-07-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bucknell C. Webb

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0056 ,  B81B2201/012 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/0015 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0109 ,  B81C2203/0136 ,  H01H59/0009 ,  H01H2001/0078

Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US20170341930A1

公开(公告)日：2017-11-30

申请号：US15650788

申请日：2017-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bucknell C. Webb

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0056 ,  B81B2201/012 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/0015 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0109 ,  B81C2203/0136 ,  H01H59/0009 ,  H01H2001/0078

Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US20170320724A1

公开(公告)日：2017-11-09

申请号：US15441887

申请日：2017-02-24

Applicant: MEMS Drive, Inc.

Inventor： Roman Gutierrez ,  Tony Tang ,  Xiaolei Liu ,  Guiqin Wang ,  Matthew NG

IPC: B81B7/00 ,  B81C1/00

CPC classification number: H01L21/76816 ,  B81B3/0045 ,  B81B7/0029 ,  B81B2203/0353 ,  B81C1/00674 ,  B81C1/00682 ,  B81C2201/0112 ,  B81C2201/0135 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/485 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/181

Abstract: A system and method for manipulating the structural characteristics of a MEMS device include etching a plurality of holes into the surface of a MEMS device, wherein the plurality of holes comprise one or more geometric shapes determined to provide specific structural characteristics desired in the MEMS device.

公开(公告)号：US09758366B2

公开(公告)日：2017-09-12

申请号：US14969329

申请日：2015-12-15

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L21/00 ,  H01L43/14 ,  H01L43/10 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81B3/0056 ,  B81B2201/012 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/0015 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0109 ,  B81C2203/0136 ,  H01H59/0009 ,  H01H2001/0078

Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US09738511B2

公开(公告)日：2017-08-22

申请号：US14225275

申请日：2014-03-25

Applicant: InvenSense, Inc.

Inventor： Jongwoo Shin ,  Kirt Reed Williams ,  Cerina Zhang ,  Kuolung (Dino) Lei

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00103 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133

Abstract: A MEMS (microelectromechanical systems) structure comprises a MEMS wafer. A MEMS wafer includes a cap with cavities bonded to a structural layer through a dielectric layer disposed between the cap and the structural layer. Unique configurations of MEMS devices and methods of providing such are set forth which provide for, in part, creating rounded, scalloped or chamfered MEMS profiles by shaping the etch mask photoresist reflow, by using a multi-step deep reactive ion etch (DRIE) with different etch characteristics, or by etching after DRIE.

公开(公告)号：US09481563B2

公开(公告)日：2016-11-01

申请号：US14644937

申请日：2015-03-11

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a micro-mechanical structure and a semiconductor material arranged over the micro-mechanical structure. A side surface of the semiconductor material includes a first region and a second region. The first region has an undulation, and the second region is a peripheral region of the side surface and decreases towards the micro-mechanical structure.

Abstract translation: 根据半导体器件的实施例，半导体器件包括布置在微机械结构上的微机械结构和半导体材料。 半导体材料的侧表面包括第一区域和第二区域。 第一区域具有起伏，第二区域是侧表面的周边区域，朝向微机械结构减小。

公开(公告)号：US20150338435A1

公开(公告)日：2015-11-26

申请号：US14818095

申请日：2015-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

IPC: G01P15/125 ,  G01P15/08 ,  B81C1/00 ,  G01C19/5719 ,  B81B3/00

CPC classification number: B81B3/0059 ,  B81B3/0056 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81C1/00158 ,  B81C1/00714 ,  B81C2201/0112 ,  B81C2201/0132 ,  G01C19/5719 ,  G01P15/0802 ,  G01P15/125

Abstract: Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed.

Abstract translation: 用于形成MEMS器件的方法和装置。 一种装置包括具有第一厚度的半导体衬底的至少一部分并被图案化以形成可移动质量块; 形成第一电容的第一板的移动感测电极; 所述至少一个锚定体从所述半导体衬底图案化并且具有形成所述第一电容的所述第二板的部分并与所述第一板间隔开第一间隙; 图案化的第二厚度的半导体材料层，以形成形成第二电容的第一板的第一电极，并进一步图案化以形成覆盖至少一个锚的第二电极，并形成间隔第二间隙的第二板，该第二间隙较小 比第一个差距; 其中形成的总电容是第一电容和第二电容之和。 公开了方法。

公开(公告)号：US08987845B2

公开(公告)日：2015-03-24

申请号：US13673223

申请日：2012-11-09

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Ting-Hau Wu ,  Kuei-Sung Chang

IPC: H01L29/84 ,  H01L27/14 ,  G01L9/00 ,  H04R23/00 ,  H01L41/332 ,  B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00531 ,  B81B3/0018 ,  B81C1/00357 ,  B81C1/0038 ,  B81C1/00595 ,  B81C1/00801 ,  B81C2201/0112 ,  H01L21/3065 ,  H01L41/332

Abstract: The present disclosure is directed to a device and its method of manufacture in which a protective region is formed below a suspended body. The protective region allows deep reactive ion etching of a bulk silicon body to form a MEMS device without encountering the various problems presented by damage to the silicon caused by backscattering of oxide during overetching periods of DRIE processes.

Abstract translation: 本发明涉及一种装置及其制造方法，其中在悬挂体下方形成保护区域。 保护区域允许体硅体的深反应离子蚀刻以形成MEMS器件，而不会遇到由DRIE工艺的过蚀刻期间的氧化物的后向散射引起的对由硅造成的损坏的各种问题。

公开(公告)号：US20150050746A1

公开(公告)日：2015-02-19

申请号：US14527039

申请日：2014-10-29

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY

Inventor： Michael D. HENRY ,  Andrew P. HOMYK ,  Axel SCHERER ,  Thomas A. TOMBRELLO ,  Sameer WALAVALKAR

IPC: G01N1/40

CPC classification number: B81C1/00111 ,  B01J19/0046 ,  B01J2219/00504 ,  B01J2219/00664 ,  B81B1/006 ,  B81B2203/0361 ,  B81B2207/056 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0159 ,  G01N1/405 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  Y10T436/25375

Abstract: Methods for fabricating of high aspect ratio probes and deforming micropillars and nanopillars are described. Use of polymers in deforming nanopillars and micropillars is also described.

Abstract translation: 描述了制造高纵横比探针和变形微柱和纳米柱的方法。 还描述了聚合物在变形纳米柱和微柱体中的使用。

公开(公告)号：US20140291779A1

公开(公告)日：2014-10-02

申请号：US13851691

申请日：2013-03-27

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: A method includes a step of performing a time multiplexed etching process, wherein the last etching step of the time multiplexed etching process is of a first time duration. After performing the time multiplexed etching process, an etching step having a second time duration is performed, wherein the second time duration is greater than the first time duration.

Abstract translation: 一种方法包括执行时间复用蚀刻工艺的步骤，其中时间复用蚀刻工艺的最后一个蚀刻步骤是第一持续时间。 在执行时间复用蚀刻处理之后，执行具有第二持续时间的蚀刻步骤，其中第二持续时间大于第一持续时间。