公开(公告)号：US3928663A

公开(公告)日：1975-12-23

申请号：US45701274

申请日：1974-04-01

Applicant: AMP INC

Inventor： REDMOND JOHN PETER ,  ANDREWS DANIEL MARSHALL ,  BROOKS CHARLES PARSONS ,  CINALLI DOMINIC A ,  MERLINA JOSEPH FRANCIS

IPC: C23C18/20 ,  H05K1/03 ,  H05K3/18 ,  C23C3/02 ,  B05D3/04

CPC classification number: C23C18/20 ,  C23C18/2013 ,  C23C18/2066 ,  C23C18/2086 ,  C23C18/22 ,  H05K1/0373 ,  H05K3/181 ,  H05K2201/0209 ,  H05K2201/0236

Abstract: A method and composition of matter useful for rendering an insulating material, self-catalytic to deposition of electroless metal from solutions thereof are shown. A base exchangeable clay material such as hectorite is base exchanged with a source of cations of a metal selected from Group I-B and VIII of the Periodic Table of Elements, preferably nickel or copper, and thereafter, the cation exchanged hectorite is heated under reducing conditions. This thermal treatment activates the exchanged hectorite as a catalyst to induce metal deposition in electroless plating baths. Without such a treatment the exchanged hectorite is not catalytic. The structure of the hectorite is altered by the thermal treatment as it no longer swells or gels when immersed in water. In addition the mechanical strength of the material is increased by the ''''sintering like'''' treatment. The modified base exchanged material can be incorporated or coated on insulating materials to provide the exterior or interior surfaces thereof with a catalytic sensitivity to deposition of electroless metal. The methods and compositions are useful in processes for manufacture of printed circuitry on substrates such as films, glass reinforced laminates, tapes, and boards. Methods of molding printed circuit substrates in desired geometrical form with vias located in predetermined pattern are disclosed along with chemical and mechanical methods of etching the surface of resin to expose base exchanged mineral that serves as the catalyst for electroless plating.

Abstract translation: 示出了用于提供绝缘材料的物质的方法和组成，其自催化以从其溶液沉积无电金属。 碱土交换性粘土材料如锂蒙脱石与选自元素周期表第I-B和VIII族的金属的阳离子源进行碱交换，优选镍或铜，然后在还原条件下加热阳离子交换的锂蒙脱石。

公开(公告)号：US3646572A

公开(公告)日：1972-02-29

申请号：US3646572D

申请日：1970-02-09

Applicant: PHOTOCIRCUITS CORP

Inventor： BURR ROBERT PAGE

IPC: C23C18/16 ,  H05K3/10 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06 ,  H05K1/02

CPC classification number: H05K3/429 ,  H05K3/103 ,  H05K3/422 ,  H05K7/06 ,  H05K2201/0236 ,  H05K2201/10287

Abstract: This invention provides a prefabricated electric wire assembly board which comprises an insulating base, a preformed, metal conductor bonded to the base, an aperture in the base intersecting the conductor such that at least one end of the conductor is exposed at the wall surrounding the aperture, and a deposit of metal on the wall which contacts and forms an integral bond with the end of the conductor.

公开(公告)号：US3628999A

公开(公告)日：1971-12-21

申请号：US3628999D

申请日：1970-03-05

Applicant: FREDERICK W SCHNEBLE JR ,  JOHN F MCCORMACK ,  RUDOLPH J ZEBLISKY ,  JOHN DUFF WILLIAMSON ,  JOSEPH POLICHETTE

Inventor： SCHNEBLE FREDERICK W JR ,  MCCORMACK JOHN F ,  ZEBLISKY RUDOLPH J ,  WILLIAMSON JOHN DUFF ,  POLICHETTE JOSEPH

IPC: H05K1/03 ,  H05K3/24 ,  H05K3/28 ,  H05K3/42 ,  B44D1/18

CPC classification number: H05K3/428 ,  H05K1/0373 ,  H05K3/243 ,  H05K3/28 ,  H05K3/42 ,  H05K2201/0236 ,  H05K2201/09436 ,  H05K2203/0571 ,  H05K2203/0577 ,  H05K2203/1383 ,  Y10T428/24322 ,  Y10T428/24917

Abstract: This invention relates to new and useful plated through hole printed circuit boards and more particularly to plated through hole printed circuit boards having highly reliable solder joints, and improved methods for producing such boards which include the application of a temporary, strippable solder mask together with a permanent solder mask.

公开(公告)号：US3560257A

公开(公告)日：1971-02-02

申请号：US3560257D

申请日：1967-01-03

Applicant: KOLLMORGEN PHOTOCIRCUITS

Inventor： SCHNEBLE FREDERICK W JR ,  LEECH EDWARD J ,  POLICHETTE JOSEPH

IPC: C23C18/16 ,  C23C18/20 ,  C23C18/40 ,  D06Q1/04 ,  H05K1/03 ,  H05K3/18 ,  H05K3/42 ,  B44D1/14 ,  B44D1/18 ,  B44D1/34

CPC classification number: H05K1/0373 ,  C23C18/1608 ,  C23C18/2086 ,  C23C18/30 ,  C23C18/40 ,  D06Q1/04 ,  H05K3/181 ,  H05K3/422 ,  H05K3/427 ,  H05K2201/0236 ,  H05K2203/121 ,  Y10T428/24322 ,  Y10T428/31696 ,  Y10T428/31699

Abstract: A METHODE FOR RENDERING INSULATING COMPOSITIONS RECEPTIVE TO THE DEPOSITION OF AN ELECTROLESS METAL IS PROVDED WHICH COMPRISES UTILIZING IN SUCH COMPOSITIONS AN ORGANIC COMPOUND OF A METAL WHICH IS A MEMBER SELECTED FROM THE METALS IN GROUPS 1-B AND 8 OF THE PERIODIC TABLE OF ELEMENTS, INCLUDING MIXTURES OF SUCH COMPOUNDS.

公开(公告)号：US20170243762A1

公开(公告)日：2017-08-24

申请号：US15588500

申请日：2017-05-05

Applicant: Intel Corporation

Inventor： Yonggang Yong LI ,  Aritra DHAR ,  Dilan SENEVIRATNE ,  Jon M. WILLIAMS

IPC: H01L21/48 ,  C23C18/38 ,  C23C18/16 ,  H01L21/288 ,  H01L23/498

CPC classification number: H01L21/4857 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/2086 ,  C23C18/30 ,  C23C18/38 ,  H01L21/288 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/107 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2203/072 ,  H05K2203/107

Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.

公开(公告)号：US20170175271A1

公开(公告)日：2017-06-22

申请号：US15448066

申请日：2017-03-02

Applicant: BYD COMPANY LIMITED

Inventor： WEI ZHOU ,  BIFENG MAO

IPC: C23C18/16 ,  C25D3/12 ,  C09D11/03 ,  C09D11/52 ,  C09D177/10 ,  C09D169/00 ,  C09D167/02 ,  C09D11/38 ,  C23C18/20 ,  C09D11/102

CPC classification number: C23C18/1612 ,  B01J23/20 ,  B01J35/0013 ,  B01J35/026 ,  B01J37/0072 ,  B01J37/08 ,  C08K3/22 ,  C08K9/02 ,  C08K2003/2231 ,  C08L77/06 ,  C09D11/03 ,  C09D11/10 ,  C09D11/102 ,  C09D11/322 ,  C09D11/38 ,  C09D11/52 ,  C09D167/02 ,  C09D169/00 ,  C09D177/10 ,  C23C18/1608 ,  C23C18/1633 ,  C23C18/1641 ,  C23C18/1646 ,  C23C18/1653 ,  C23C18/1655 ,  C23C18/1893 ,  C23C18/20 ,  C23C18/204 ,  C23C18/2066 ,  C23C18/40 ,  C25D3/12 ,  H05K3/182 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2203/0709 ,  H05K2203/107

Abstract: Provided is a doped tin oxide that can be used as a chemical plating promoter in a method for selectively metallizing a surface of an insulating substrate. Also provided are a polymer composition that includes the doped tin oxide, a polymer molded body, an ink composition, and a method for selectively metallizing a surface of an insulating substrate. The doped tin oxide has a light color, and does not interfere with the color of the substrate while presetting thereof. The doped tin oxide has a strong ability of promoting chemical plating. Using the disclosed doped tin oxide as a chemical plating promoter, a continuous metal layer can be formed with a high plating speed, together with enhanced adhesivity between the metal layer and the insulating substrate.

公开(公告)号：US20170048974A1

公开(公告)日：2017-02-16

申请号：US15306300

申请日：2015-03-19

Applicant: TAIYO INK MFG. CO., LTD.

Inventor： Touko SHIINA ,  Shoji MINEGISHI

IPC: H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0353 ,  H05K1/0298 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/184 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4602 ,  H05K2201/0212 ,  H05K2201/0236

Abstract: A resin composition for a permanent insulating film is provided, by which, in particular, partial through-holes obtained by partitioning a through-hole can be easily and precisely formed as designed without a deposition of catalytic species (seed) in a plating resist portion. The present invention provides a resin composition for a permanent insulating film, including a thermosetting resin, a resin filler, and a compound containing at least one atom selected from a sulfur atom and a nitrogen atom. The present invention also provides a multilayer printed wiring board in which conductive layers having a circuit pattern and insulation layers are alternately overlaid with each other, and a through-hole enabling electric conductivity among conductive layers via a through-hole. The through-hole includes a plating resist portion provided on either of an interlaminar part between the conductive layer and the insulation layer or another interlaminar part between the insulation layers, or both. The plating portion(s) is/are provided on the interlaminar parts which had been exposed in an opening as the through-hole, and on an exposed region other than the plating resist portion, and the plating resist portion is made of a cured product of the resin composition.

Abstract translation: 提供了一种用于永久绝缘膜的树脂组合物，特别地，通过分隔通孔获得的部分通孔可以容易且精确地形成，而不会在电镀抗蚀剂部分中沉积催化物质（种子） 。 本发明提供一种用于永久绝缘膜的树脂组合物，其包含热固性树脂，树脂填料和含有至少一个选自硫原子和氮原子的原子的化合物。 本发明还提供一种多层印刷布线板，其中具有电路图案和绝缘层的导电层彼此交替地叠置，并且通孔经由通孔使导电层之间能够导电。 通孔包括设置在导电层和绝缘层之间的层间部分之间或绝缘层之间的另一层间部分或两者之间的电镀抗蚀剂部分。 电镀部分设置在作为通孔的开口中露出的层间部分上，以及在电镀抗蚀剂部分以外的暴露区域上，并且电镀抗蚀部分由固化产物 的树脂组合物。

公开(公告)号：US09508634B2

公开(公告)日：2016-11-29

申请号：US15133244

申请日：2016-04-20

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/495 ,  H01L21/768 ,  H05K1/03 ,  H05K3/18 ,  H05K3/40 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10 ,  H05K3/46

CPC classification number: H01L23/49586 ,  H01L21/4828 ,  H01L21/76823 ,  H01L21/76825 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2924/181 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a metal stud array having metal studs. The selective-electroplating epoxy compound covers the metal stud array. The selective-electroplating epoxy compound includes non-conductive metal complex. The conductive vias are directly embedded in the selective electroplating epoxy compound to be respectively connected to the metal studs and extended to a top surface of the selective-electroplating epoxy compound. Each of the conductive vias includes a lower segment connected to the corresponding metal stud and an upper segment connected to the lower segment and extended to the top surface, and a smallest diameter of the upper segment is greater than a largest diameter of the lower segment. The patterned circuit layer is directly disposed on the top surface and electrically connected to the conductive vias.

Abstract translation: 封装结构包括引线框，选择性电镀环氧化合物，导电通孔和图案化电路层。 引线框架包括具有金属螺柱的金属螺柱阵列。 选择性电镀环氧化合物覆盖金属螺柱阵列。 选择性电镀环氧化合物包括非导电金属络合物。 导电通孔直接嵌入选择性电镀环氧化合物中，以分别连接到金属螺柱并延伸到选择性电镀环氧化合物的顶表面。 每个导电通孔包括连接到相应的金属螺柱的下部段和连接到下部段并延伸到顶部表面的上段，并且上段的最小直径大于下段的最大直径。 图案化电路层直接设置在顶表面上并电连接到导电通孔。

公开(公告)号：US20160295708A1

公开(公告)日：2016-10-06

申请号：US15184426

申请日：2016-06-16

Applicant: SIERRA CIRCUITS, INC.

Inventor： Konstantine Karavakis ,  Kenneth S. Bahl

IPC: H05K3/42 ,  H05K3/00 ,  H05K3/38 ,  H05K1/09 ,  H05K1/11

CPC classification number: H05K3/426 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/387 ,  H05K2201/0221 ,  H05K2201/0236 ,  H05K2203/0709 ,  Y10T29/49167

Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.

公开(公告)号：US09210815B2

公开(公告)日：2015-12-08

申请号：US13474735

申请日：2012-05-18

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H05K3/36 ,  H05K3/00 ,  H05K3/46 ,  H05K3/10

CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

Abstract: A manufacturing method of an embedded wiring board is provided. The method includes the following steps. First, an insulation layer and a lower wiring layer are provided, wherein the insulation layer includes a polymeric material. Then, the plural catalyst grains are distributed in the polymeric material. A groove and an engraved pattern are formed on the upper surface. A blind via is formed on a bottom surface of the groove to expose the lower pad. An upper wiring layer is formed in the engraved pattern. Some catalyst grains are exposed and activated in the groove, the engraved pattern and the blind via. A first conductive pillar is formed in the groove. Finally, a second conductive pillar is formed in the blind via.

Abstract translation: 提供了一种嵌入式布线板的制造方法。 该方法包括以下步骤。 首先，提供绝缘层和下布线层，其中绝缘层包括聚合材料。 然后，多个催化剂颗粒分布在聚合物材料中。 在上表面上形成有凹槽和雕刻图案。 在槽的底表面上形成盲孔以露出下垫。 上部布线层形成在雕刻图案中。 一些催化剂颗粒在凹槽，雕刻图案和盲孔中暴露和活化。 第一导电柱形成在凹槽中。 最后，在盲通孔中形成第二导电柱。