公开(公告)号：US20150016049A1

公开(公告)日：2015-01-15

申请号：US14386637

申请日：2013-03-20

Applicant: LG INNOTEK CO., LTD.

Inventor： Seol Hee Lim

IPC: H05K1/05

CPC classification number: H05K1/05 ,  C25D3/14 ,  C25D3/16 ,  C25D5/022 ,  C25D5/12 ,  H01L2224/45144 ,  H01L2224/48091 ,  H05K1/11 ,  H05K1/117 ,  H05K1/181 ,  H05K3/244 ,  H05K2201/0104 ,  H05K2201/032 ,  H05K2201/0338 ,  H05K2201/10159 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A printed circuit board for a memory card includes an insulating layer; a mounting part on a first surface of the insulating layer, the mounting part being electrically connected to a memory device; and a terminal part on a second surface of the insulating layer, the terminal part being electrically connected to an external electronic appliance, wherein a same metal layer having a same property is formed on exposed surfaces of the mounting part and the terminal part.

Abstract translation: 用于存储卡的印刷电路板包括绝缘层; 绝缘层的第一表面上的安装部分，所述安装部分电连接到存储装置; 以及在所述绝缘层的第二表面上的端子部分，所述端子部分电连接到外部电子设备，其中在所述安装部分和所述端子部分的暴露表面上形成具有相同特性的相同金属层。

公开(公告)号：US20150014030A1

公开(公告)日：2015-01-15

申请号：US14467680

申请日：2014-08-25

Applicant: FUJIFILM Corporation

Inventor： Yasuhiro MITAMURA ,  Masaya NAKAYAMA ,  Yuki MATSUNAMI

IPC: H05K1/02 ,  H05K1/09 ,  H01B3/44

CPC classification number: H05K1/0256 ,  B32B3/08 ,  B32B5/024 ,  B32B7/12 ,  B32B15/08 ,  B32B27/20 ,  B32B27/281 ,  B32B27/283 ,  B32B27/30 ,  B32B27/308 ,  B32B27/32 ,  B32B27/322 ,  B32B27/36 ,  B32B27/38 ,  B32B27/42 ,  B32B2255/205 ,  B32B2260/021 ,  B32B2260/046 ,  B32B2262/0269 ,  B32B2262/101 ,  B32B2307/202 ,  B32B2307/412 ,  B32B2457/00 ,  C08K5/378 ,  C08K5/47 ,  H01B3/447 ,  H05K1/092 ,  H05K3/285 ,  H05K2201/0108 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/0206 ,  H05K2201/032 ,  H05K2201/0769 ,  Y10T428/2804

Abstract: A composition for forming a silver ion diffusion-suppressing layer includes an insulating resin and a compound including: a structure selected from the group consisting of a triazole structure, a thiadiazole structure and a benzimidazole structure; a mercapto group; and at least one hydrocarbon group optionally containing a heteroatom, with the total number of carbon atoms in the hydrocarbon group or groups being 5 or more. The composition for forming a silver ion diffusion-suppressing layer allows formation of a silver ion diffusion-suppressing layer capable of suppressing silver ion migration between metal interconnects containing silver or a silver alloy to improve the reliability on the insulation between the metal interconnects.

Abstract translation: 用于形成银离子扩散抑制层的组合物包括绝缘树脂和包含选自三唑结构，噻二唑结构和苯并咪唑结构的结构的化合物; 巯基; 和至少一个任选含有杂原子的烃基，烃基或碳原子数的总数为5以上。 用于形成银离子扩散抑制层的组合物允许形成能够抑制银或银合金的金属互连之间的银离子迁移的银离子扩散抑制层，以提高金属互连之间的绝缘的可靠性。

公开(公告)号：US20150008016A1

公开(公告)日：2015-01-08

申请号：US14360904

申请日：2014-04-03

Applicant: Nuovo Film, Inc.

Inventor： Hakfei Poon

IPC: H05K1/09 ,  H05K1/02 ,  H05K1/03

CPC classification number: H01B13/30 ,  G06F3/041 ,  G06F2203/04103 ,  G06F2203/04112 ,  H01B1/02 ,  H01B1/22 ,  H01L31/022466 ,  H01L31/1884 ,  H05K1/0274 ,  H05K1/0298 ,  H05K1/03 ,  H05K1/09 ,  H05K2201/0302 ,  H05K2201/032

Abstract: Discloses herein is a patterned transparent conductive electrode, comprises a substrate and a substantial single conductive layer on top of the substrate. The single conductive layer comprises a first region comprising a network of silver nanowires and means for protecting the nanowire from surface oxidation; and a second region, comprising a plurality of metal nanowires and means for protecting nanowire from surface oxidation, and metal oxide nanowires.

Abstract translation: 本发明公开了一种图案化的透明导电电极，其包含衬底和在衬底顶部上的基本单个导电层。 单个导电层包括包含银纳米线网络的第一区域和用于保护纳米线免受表面氧化的装置; 以及包括多个金属纳米线的第二区域和用于保护纳米线免受表面氧化的装置和金属氧化物纳米线。

公开(公告)号：US20140332259A1

公开(公告)日：2014-11-13

申请号：US14444135

申请日：2014-07-28

Applicant: TOPPAN PRINTING CO., LTD. ,  NATIONAL UNIVERSITY CORPORATION GUNMA UNIVERSITY

Inventor： Tetsuyuki TSUCHIDA ,  Toshikazu OKUBO ,  Ikuo SHOHJI ,  Takahiro KANO

IPC: H05K1/09 ,  C23C18/36 ,  H05K3/24

CPC classification number: H05K1/09 ,  C23C18/1651 ,  C23C18/36 ,  C23C18/44 ,  C23C18/50 ,  H05K3/243 ,  H05K3/244 ,  H05K2201/032 ,  H05K2201/0776 ,  H05K2203/072

Abstract: A wiring substrate includes an electrode including Cu or a Cu alloy, and a plated film including an electroless nickel-plated layer formed on the electrode and an electroless gold-plated layer formed on the electroless nickel-plated layer. The electroless nickel-plated layer is formed by co-precipitation of Ni, P, Bi, and S, the electroless nickel-plated layer includes a content of P of 5% by mass or more and less than 10% by mass, a content of Bi of 1 ppm by mass to 1,000 ppm by mass, and a content of S of 1 ppm by mass to 2,000 ppm by mass, and a mass ratio of the content of S to the content of Bi (S/Bi) is more than 1.0.

Abstract translation: 布线基板包括包含Cu或Cu合金的电极和形成在电极上的化学镀镍层和形成在化学镀镍层上的化学镀金层的镀膜。 化学镀镍层通过Ni，P，Bi和S的共沉淀形成，无电镀镍层的P含量为5质量％以上且小于10质量％，含量 的Bi为1质量ppm〜1000质量ppm，S为1质量ppm〜2000质量ppm，S含量与Bi（S / Bi）含量的质量比为更多 比1.0。

公开(公告)号：US20240349423A1

公开(公告)日：2024-10-17

申请号：US18682745

申请日：2022-05-30

Applicant: GUANGZHOU FANGBANG ELECTRONICS CO., LTD

Inventor： Meijuan Zhang ,  Yuhua Zhu

IPC: H05K1/09 ,  H05K3/06

CPC classification number: H05K1/09 ,  H05K3/064 ,  H05K2201/032 ,  H05K2201/0338 ,  H05K2201/0355

Abstract: The present disclosure relates to the technical field of metal foils. Disclosed is a metal foil, including a conductive layer and a bearing layer, the conductive layer and the bearing layer being stacked. The conductive layer is configured to manufacture a conductive line. When a circuit board is manufactured using the metal foil, the bearing layer is separated from the conductive layer by a first etching solution, and a roughness Rz of a surface, close to the conductive layer, of the bearing layer is less than or equal to 2 microns. When the circuit board is manufactured using the metal foil, a surface of the conductive line is substantially flush with a surface of a substrate after the bearing layer is removed, and the surface roughness of the conductive line is low, so that the product requirement for high dimensional accuracy may be satisfied. Meanwhile, embodiments of the present disclosure further correspondingly provide a circuit board and a method for manufacturing the circuit board.

公开(公告)号：US20240324103A1

公开(公告)日：2024-09-26

申请号：US18613202

申请日：2024-03-22

Applicant: IBIDEN CO., LTD.

Inventor： Masashi KUWABARA ,  Jun SAKAI ,  Shiho FUKUSHIMA

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/16

CPC classification number: H05K1/115 ,  H05K1/0306 ,  H05K3/16 ,  H05K2201/0209 ,  H05K2201/0242 ,  H05K2201/0266 ,  H05K2201/032 ,  H05K2201/09536

Abstract: A wiring substrate includes a core substrate including a through-hole conductor, a first resin insulating layer, a first conductor layer including a seed layer and an electrolytic plating layer, a via conductor formed such that the via conductor electrically connects the through-hole conductor and first conductor layer, and a second resin insulating layer covering the first conductor layer. The core substrate includes a glass substrate such that the through-hole conductor is penetrating through the glass substrate, the seed layer includes a first layer formed on the first resin insulating layer and a second layer formed on the first layer, and the first conductor layer includes a conductor circuit such that a width of the first layer is larger than a width of the second layer in the conductor circuit and a width of the electrolytic plating layer is larger than the width of the first layer in the conductor circuit.

公开(公告)号：US20240306299A1

公开(公告)日：2024-09-12

申请号：US18595674

申请日：2024-03-05

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki FURUTANI ,  Kyohei YOSHIKAWA ,  Takuya INISHI ,  Jun SAKAI

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/16 ,  H05K3/18

CPC classification number: H05K1/116 ,  H05K1/0306 ,  H05K3/181 ,  H05K3/16 ,  H05K2201/032 ,  H05K2201/09536

Abstract: A wiring substrate includes a core substrate including a through-hole conductor, a resin insulating layer formed on the core substrate, a conductor layer formed on a surface of the resin insulating layer and including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor formed in the resin insulating layer such that the via conductor is connected to the through-hole conductor in the core substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer. The core substrate includes a glass substrate such that the through-hole conductor is formed in a through hole penetrating through the glass substrate, and the conductor layer and via conductor are formed such that the seed layer is formed by sputtering and includes an alloy including copper, aluminum, and one or more metals selected from nickel, zinc, gallium, silicon, and magnesium.

公开(公告)号：US12082334B2

公开(公告)日：2024-09-03

申请号：US17720685

申请日：2022-04-14

Applicant: Hamilton Sundstrand Corporation

Inventor： John Dickey ,  Kevin Kilroy

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/18 ,  H05K3/10

CPC classification number: H05K1/0207 ,  H05K1/021 ,  H05K1/09 ,  H05K1/181 ,  H05K3/107 ,  H05K2201/0302 ,  H05K2201/032 ,  H05K2201/10166

Abstract: Circuit board assemblies include a circuit board portion having a recess formed therein, an electrically and thermally conductive insert, shaped to fit in the recess formed in the circuit board portion, an electrically and thermally conductive layer adapted and configured to interface with an external chassis, and a thermally conductive electrically insulative portion interposed between the electrically and thermally conductive insert and the electrically and thermally conductive layer, adapted and configured to conduct heat from the electrically and thermally conductive insert to the electrically and thermally conductive layer without conducting electricity.

公开(公告)号：US20230189444A1

公开(公告)日：2023-06-15

申请号：US17955683

申请日：2022-09-29

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Gao HUANG ,  Benxia HUANG ,  Yejie HONG

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K1/186 ,  H05K1/113 ,  H05K1/0366 ,  H05K3/0035 ,  H05K3/4661 ,  H05K3/429 ,  H05K2201/032 ,  H05K2201/09509 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2203/061 ,  H05K2203/308

Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.

公开(公告)号：US20180376593A1

公开(公告)日：2018-12-27

申请号：US16118212

申请日：2018-08-30

Applicant: Korea Electronics Technology Institute

Inventor： Yoonjin Kim ,  Jinwoo Cho ,  Kwonwoo Shin ,  Yonggon Seo ,  Yeonwon Kim ,  Sanghyeon Jang ,  Namje Jo

IPC: H05K1/09 ,  B22F1/00 ,  B22F1/02 ,  H05K3/12 ,  H05K3/02 ,  C09D11/037 ,  H01B1/20 ,  C09D11/52 ,  B22F9/24 ,  H01B1/22 ,  H05K3/22

CPC classification number: H05K1/095 ,  B22F1/0022 ,  B22F1/0074 ,  B22F1/02 ,  B22F9/24 ,  B22F2301/10 ,  B22F2302/25 ,  C09D11/037 ,  C09D11/52 ,  H01B1/20 ,  H01B1/22 ,  H05K1/097 ,  H05K3/027 ,  H05K3/1216 ,  H05K3/227 ,  H05K2201/032

Abstract: The present invention provides a method of fabricating a wiring board and a wiring board fabricated by the method, the method including a step of screen-printing the ink composition for light sintering on a flexible board body to form a preliminary wiring pattern, a step of drying the preliminary wiring pattern, and a step of reducing and sintering the oxidized copper of the copper oxide nanoparticles, which are included in the preliminary wiring pattern, by irradiating the dried preliminary wiring pattern with light to form a wiring pattern on the board body.