公开(公告)号：US07803515B2

公开(公告)日：2010-09-28

申请号：US11556384

申请日：2006-11-03

Applicant: Toshimitsu Hirai ,  Katsuyuki Moriya

Inventor： Toshimitsu Hirai ,  Katsuyuki Moriya

IPC: H01L21/00

CPC classification number: H05K3/1258 ,  G02F2001/136295 ,  H05K3/125 ,  H05K2201/09272 ,  H05K2201/09727 ,  H05K2203/013 ,  H05K2203/0568

Abstract: A method for forming a film pattern by disposing a functional fluid on a substrate, includes: forming a partition wall that includes a first opening that corresponds to a first film pattern and a second opening that corresponds to a second film pattern; and disposing a droplet of the functional fluid into the first opening, so that the functional fluid is disposed into the second opening by a self-flow of the functional fluid; wherein: the first film pattern is linear; the second film pattern is narrower than the first film pattern, and is connected to the first film pattern at a rear edge thereof; and a front edge of the second film pattern has a missing part in which a corner of a rectangular contour is missing.

Abstract translation: 通过在基板上设置功能流体来形成膜图案的方法包括：形成分隔壁，其包括对应于第一膜图案的第一开口和对应于第二膜图案的第二开口; 并且将所述功能流体液滴设置在所述第一开口中，使得所述功能流体通过所述功能流体的自身流动而被设置在所述第二开口中; 其中：所述第一膜图案是线性的; 所述第二胶片图案比所述第一胶片图案窄，并且在其后缘与所述第一胶片图案连接; 并且第二胶片图案的前边缘具有缺少矩形轮廓的角部的缺失部分。

公开(公告)号：US07429902B2

公开(公告)日：2008-09-30

申请号：US11980616

申请日：2007-10-31

Applicant: Hiroshi Kanno ,  Kazuyuki Sakiyama ,  Ushio Sangawa ,  Tomoyasu Fujishima

Inventor： Hiroshi Kanno ,  Kazuyuki Sakiyama ,  Ushio Sangawa ,  Tomoyasu Fujishima

IPC: H01P3/08

CPC classification number: H01P3/081 ,  H05K1/0245 ,  H05K1/0253 ,  H05K2201/09272

Abstract: A differential transmission line includes: a substrate; a ground conductor layer; and a first and a second signal conductor disposed in parallel to each other on the substrate. The first signal conductor and the ground conductor layer compose a first transmission line, whereas the second signal conductor and the ground conductor layer compose a second transmission line. The first transmission line and the second transmission line compose a differential transmission line. The differential transmission line includes a curved region, with a straight region being connected to each end of the curved region. In the ground conductor layer in the curved region, a plurality of slots orthogonal to a local transmission direction of signals in the curved region are formed, and the slots are connected to one another on the inner side of the curvature.

Abstract translation: 差动传输线包括：基板; 接地导体层; 以及在基板上彼此平行设置的第一和第二信号导体。 第一信号导体和接地导体层构成第一传输线，而第二信号导体和接地导体层构成第二传输线。 第一传输线和第二传输线构成差动传输线。 差动传输线包括弯曲区域，直线区域连接到弯曲区域的每一端。 在弯曲区域的接地导体层中，形成与弯曲区域中的信号的局部传输方向正交的多个槽，并且在曲率的内侧上彼此连接。

公开(公告)号：US07408256B2

公开(公告)日：2008-08-05

申请号：US11535115

申请日：2006-09-26

Applicant: Kohji Shinomiya

Inventor： Kohji Shinomiya

IPC: H01L23/52

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: An integrated circuit chip module includes a first integrated circuit chip including a first power source pad for a first power voltage and an adjacent second power source pad for a second power voltage, the first power voltage being higher than the second power voltage, a second integrated circuit chip including a third power source pad for the first power voltage and an adjacent fourth power source pad for the second power voltage, and a wiring board including a first power source wire electrically connected to the first power source pad, a second power source wire electrically connected to the second power source pad, a third power source wire electrically connected to the third power source pad, and a fourth power source wire electrically connected to the fourth power source pad. Distance between the first and second power source wires is shorter than distance between the first or second power source wires and the third or fourth power source wires, and distance between the third and fourth power source wires is shorter than distance between the first or second power source wires and the third or fourth power source wires.

Abstract translation: 集成电路芯片模块包括第一集成电路芯片，其包括用于第一电源电压的第一电源焊盘和用于第二电源电压的相邻的第二电源焊盘，所述第一电源电压高于所述第二电源电压，第二集成电路 电路芯片，包括用于第一电源电压的第三电源焊盘和用于第二电源电压的相邻第四电源焊盘;以及布线板，包括电连接到第一电源焊盘的第一电源线，第二电源线 电连接到第二电源焊盘，电连接到第三电源焊盘的第三电源线和电连接到第四电源焊盘的第四电源线。 第一和第二电源线之间的距离短于第一或第二电源线与第三或第四电源线之间的距离，并且第三和第四电源线之间的距离短于第一或第二电源线之间的距离 源极线和第三或第四电源线。

公开(公告)号：US20080116989A1

公开(公告)日：2008-05-22

申请号：US11980616

申请日：2007-10-31

Applicant: Hiroshi Kanno ,  Kazuyuki Sakiyama ,  Ushio Sangawa ,  Tomoyasu Fujishima

Inventor： Hiroshi Kanno ,  Kazuyuki Sakiyama ,  Ushio Sangawa ,  Tomoyasu Fujishima

IPC: H01P3/08

CPC classification number: H01P3/081 ,  H05K1/0245 ,  H05K1/0253 ,  H05K2201/09272

Abstract: A differential transmission line includes: a substrate; a ground conductor layer; and a first and a second signal conductor disposed in parallel to each other on the substrate. The first signal conductor and the ground conductor layer compose a first transmission line, whereas the second signal conductor and the ground conductor layer compose a second transmission line. The first transmission line and the second transmission line compose a differential transmission line. The differential transmission line includes a curved region, with a straight region being connected to each end of the curved region. In the ground conductor layer in the curved region, a plurality of slots orthogonal to a local transmission direction of signals in the curved region are formed, and the slots are connected to one another on the inner side of the curvature.

Abstract translation: 差动传输线包括：基板; 接地导体层; 以及在基板上彼此平行设置的第一和第二信号导体。 第一信号导体和接地导体层构成第一传输线，而第二信号导体和接地导体层构成第二传输线。 第一传输线和第二传输线构成差动传输线。 差动传输线包括弯曲区域，直线区域连接到弯曲区域的每一端。 在弯曲区域的接地导体层中，形成与弯曲区域中的信号的局部传输方向正交的多个槽，并且在曲率的内侧上彼此连接。

公开(公告)号：US20040065962A1

公开(公告)日：2004-04-08

申请号：US10395382

申请日：2003-03-25

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Kohji Shinomiya

IPC: H01L023/48

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: On the circuit surfaces of integrated circuit chips, there are adjacently laid out a power source pad for a power source wire at a plus voltage side and a power source pad for a power source wire at a minus voltage side. On a single-surface printed wiring board, a first set of two power source wires and a second set of two power source wires are flip-chip mounted with two power source pads of the integrated circuit chips respectively. The first and second sets of the power source wires are formed substantially in parallel with each other, by maintaining substantially constant wire widths and substantially constant wire interval. Near the outer periphery of the printed wiring board, the first and second sets of the power source wires are bent smoothly to follow the periphery.

Abstract translation: 在集成电路芯片的电路面上，相邻设置用于正电压侧的电源线的电源焊盘和负电压侧的电源线的电源焊盘。 在单面印刷电路板上，第一组两根电源线和第二组两根电源线分别与集成电路芯片的两个电源焊盘一起倒装芯片。 第一组和第二组电源线通过保持基本上恒定的导线宽度和基本上恒定的导线间隔而彼此基本上彼此平行地形成。 在印刷电路板的外周附近，第一和第二组电源线平滑地弯曲以跟随周边。

公开(公告)号：US5858591A

公开(公告)日：1999-01-12

申请号：US17407

申请日：1998-02-02

Applicant: Chia Hui Lin ,  San-De Tzu ,  Chih-Chiang Tu

Inventor： Chia Hui Lin ,  San-De Tzu ,  Chih-Chiang Tu

IPC: G03F1/00 ,  H05K3/00 ,  G03F9/00 ,  G03C5/00

CPC classification number: H05K3/0005 ,  G03F1/36 ,  H05K2201/09272 ,  H05K3/0082

Abstract: Improvement in the quality of photoresist images has been achieved. The data file in which the full description of the photoresist image, including Optical Proximity Corrections, has been stored is split into two subfiles. The split is made on the basis of separating cell descriptions (where the density of lines is high) from peripheral area descriptions (where lines tend to be isolated). A suitable bias in the form of a small increase or decrease (as appropriate) of all dimensions in the subfile is then applied. After the application of bias, the subfiles are merged back into a single data file and processing proceeds as usual.

Abstract translation: 已经实现了光刻胶图像质量的提高。 已经存储了包括光学邻近校正的光致抗蚀剂图像的完整描述的数据文件被分成两个子文件。 分割是基于从周边区域描述（其中线路被孤立的）分离单元描述（其中线的密度高）的基础。 然后应用子文件中所有维度的小增加或减小（适当时）形式的合适偏差。 应用偏倚之后，子文件被合并回单个数据文件，处理按照惯例进行。

公开(公告)号：US5449863A

公开(公告)日：1995-09-12

申请号：US220257

申请日：1994-03-30

Applicant: Fumio Nakatani ,  Shinichi Wakita ,  Hisatoshi Murakami ,  Tsunehiko Terada ,  Shohei Morimoto

Inventor： Fumio Nakatani ,  Shinichi Wakita ,  Hisatoshi Murakami ,  Tsunehiko Terada ,  Shohei Morimoto

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K3/34 ,  H05K3/46 ,  H05K9/00 ,  H05K1/00

CPC classification number: H05K1/0216 ,  H05K1/0218 ,  H05K1/162 ,  H05K9/0039 ,  H05K1/095 ,  H05K1/117 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09272 ,  H05K2201/09672 ,  H05K2201/10689 ,  H05K3/3447 ,  H05K3/4644 ,  H05K3/4664 ,  Y10S428/901

Abstract: The radiation noise suppression effect is enhanced by providing an insulation layer which is formed so that the circuit pattern is covered excepting at least a part of power source pattern or ground pattern on the substrate on which circuit pattern is formed, and a conductive layer which is formed so as to be connected to the uninsulated part of the power source pattern or the ground pattern on the insulation layer, by modifying pattern shape of the conductive layer and the insulation layer or by increasing or reducing the number of these layers.

Abstract translation: 辐射噪声抑制效果通过提供形成为使得电路图案被覆盖的绝缘层，除了在其上形成电路图案的基板上的至少一部分电源图案或接地图案之外，导电层是 通过改变导电层和绝缘层的图案形状，或者通过增加或减少这些层的数量，形成为连接到电源图案的未绝缘部分或绝缘层上的接地图案。

公开(公告)号：US5373628A

公开(公告)日：1994-12-20

申请号：US950132

申请日：1992-09-24

Applicant: Akihiko Suehiro ,  Tsuneo Oka

Inventor： Akihiko Suehiro ,  Tsuneo Oka

IPC: G06F17/50 ,  H05K3/00 ,  H05K13/06 ,  H01K3/10

CPC classification number: H05K13/06 ,  G06F17/5077 ,  H05K3/0005 ,  H05K2201/09272 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/532

Abstract: An automatic wiring method includes a first step of finding locations at which diagonal wiring is required at the time of wiring processing, a second step of approximating the shapes of part pins associated with these locations by rectangular shapes and reducing and changing these approximated shapes into shapes capable of being wired by 90.degree. turns, a third step of executing automatic wiring processing for 90.degree. turns, a fourth step of finding a location at which a clearance between a wiring pattern obtained by the wiring processing for 90.degree. turns and an actual part pin becomes less than a stipulated value and a clearance error is generated, and a fifth step of shaping a 90.degree.-turn wiring pattern at this location into a diagonal wiring pattern so as to satisfy the clearance.

Abstract translation: 一种自动布线方法包括：第一步骤，在布线处理时找到需要对角布线的位置;第二步骤，用矩形形状近似与这些位置相关联的部分针脚的形状，并将这些近似形状缩小并变换成形状 能够进行90°线的接线，第三步执行90°的自动布线处理，第四步，找到通过90°线路加工得到的布线图案之间的间隙与实际部分 销变得小于规定值并产生间隙误差，并且将该位置处的90°折线布线图案成形为对角线布线图案以满足间隙的第五步骤。

公开(公告)号：US4679121A

公开(公告)日：1987-07-07

申请号：US864418

申请日：1986-01-24

Applicant: Josef Schomers ,  Kurt Erbele ,  Wernfried Bonk

Inventor： Josef Schomers ,  Kurt Erbele ,  Wernfried Bonk

IPC: H05K1/02 ,  H05K7/14 ,  H05K1/14

CPC classification number: H05K1/0228 ,  H05K7/1439 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09272 ,  H05K2201/09709

Abstract: An electrical device assembly system composed of plug-in circuit boards each having a plurality of plug-in connectors at an edge presenting input and output terminals. Magazines each mounting a plurality of the circuit boards are provided. The magazines each have a rear side and are disposed adjacent to one another. Each plurality of plug-in circuit boards are mounted in a respective one of the magazines so that the plug-in connectors are located at the rear side. Rear wall circuit boards are fastened to the rear sides of the magazines and include plug-in counterconnectors for mating with corresponding ones of the plug-in connectors at the edges of the plug-in circuit boards. The plug-in connectors of each plurality of plug-in circuit boards define separate regions at the rear side of each magazine. At least one rear wall circuit board is fastened to two adjacent magazines and covers two adjacent ones of the regions, one each from the two adjacent magazines. The plug-in counterconnectors each have a plurality of electrical contacts corresponding to the input and output terminals, respectively, of the plug-in connectors. The rear wall circuit board includes conductor paths between selected contacts for forming the electrical connections between the input and output terminals. Respective ones of the input and output terminals of each plug-in circuit board are associated with the connector of the plurality of connectors which is closest to the adjacent magazine to which the respective ones of the input and output terminals are connected.

Abstract translation: 一种由插入式电路板组成的电气装置组装系统，每个插入式电路板在呈现输入和输出端子的边缘处具有多个插入式连接器。 提供了各自安装多个电路板的各种杂志。 杂志各自具有后侧并且彼此相邻地设置。 每个插入式电路板安装在相应的一个杂志中，使得插入式连接器位于后侧。 后壁电路板被固定到杂志的后侧，并且包括用于与插入式电路板的边缘处的相应的插入式连接器配合的插入式计数器连接器。 每个插入式电路板的插入式连接器在每个盒的后侧限定分开的区域。 至少一个后墙电路板固定到两个相邻的杂志上，并覆盖两个相邻的区域，每个杂志分别来自两个相邻的杂志。 插入式计数器连接器各自具有分别对应于插入式连接器的输入和输出端子的多个电触点。 后壁电路板包括用于形成输入和输出端子之间的电连接的所选触点之间的导体路径。 每个插入式电路板的输入和输出端子中的相应输入和输出端子与多个连接器的连接器相关联，该连接器最靠近相应的输入和输出端子连接到相邻的盒体。

公开(公告)号：US11653441B2

公开(公告)日：2023-05-16

申请号：US16951695

申请日：2020-11-18

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Julien Didion ,  Thierry Lapergue

IPC: H05K1/02 ,  H04B1/16 ,  H05K1/18

CPC classification number: H05K1/025 ,  H04B1/16 ,  H05K1/181 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10045 ,  H05K2201/10098

Abstract: A device includes a printed circuit board substrate, an antenna connected to the printed circuit board substrate, an amplifier connected to the printed circuit board substrate, and a matching track having a first end electrically connected to an input of the amplifier and a second end electrically connected to an output of the antenna. The matching track has an outgrowth that is symmetrical along a median axis of the outgrowth. The matching track is rectilinear and has a constant width over an initial part extending between the widening area and the first end. A median axis of the initial part and the median axis of the outgrowth form an angle comprised between 60 and 120°.