公开(公告)号：EP1238431B1

公开(公告)日：2015-04-01

申请号：EP00993460.5

申请日：2000-12-12

Applicant: 3D Plus

Inventor： Val, Christian Thales Intellectual Property

IPC: H01L23/522 ,  H05K1/18 ,  H05K3/40 ,  H05K1/02 ,  H05K3/04

CPC classification number: H01L25/50 ,  H01L23/5222 ,  H01L24/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/184 ,  H05K1/185 ,  H05K3/045 ,  H05K3/403 ,  H05K2201/0715 ,  H05K2201/09181 ,  H05K2201/09645 ,  H05K2201/10643 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2924/00

公开(公告)号：EP2705531A2

公开(公告)日：2014-03-12

申请号：EP12718241.8

申请日：2012-05-04

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/538 ,  H01L21/60 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01G4/224 ,  B05D1/02 ,  B05D5/10 ,  C23C14/08 ,  C23C16/01 ,  C23C16/402 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/18 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68368 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/115 ,  H05K1/181 ,  H05K3/284 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

Abstract: The invention relates to a method for the collective production of a reconstituted wafer that comprises chips with connection pads on a so-called front side of the chip, said method comprising a step of: A) placing the chips on an initial adhesive carrier, front side on the carrier, characterized in that it comprises the following steps: B) depositing, in the gaseous phase at atmospheric pressure and at room temperature, an electrically insulating layer on the initial carrier and the chips, this layer having a mechanical role in supporting the chips; C) transferring the chips covered with the mineral layer to a temporary adhesive carrier, the rear side of the chips facing the temporary adhesive carrier; D) removing the initial adhesive carrier; E) placing the chips on a chuck, the front sides of the chips facing the chuck; F) removing the temporary adhesive carrier; G) depositing a resin over the chuck so as to encapsulate the chips, then curing the resin; H) removing the chuck; and I) producing an RDL on the active side.

公开(公告)号：EP2684434A1

公开(公告)日：2014-01-15

申请号：EP12708973.8

申请日：2012-03-06

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  3D Plus

Inventor： LIMOUSIN, Olivier ,  SOUFFLET, Fabrice

IPC: H05K3/32 ,  H05K3/40 ,  H01L21/60

CPC classification number: H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/27003 ,  H01L2224/2711 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/12042 ,  H05K3/027 ,  H05K3/06 ,  H05K3/12 ,  H05K3/321 ,  H05K3/4007 ,  H05K2201/10674 ,  H05K2203/107 ,  H05K2203/1476 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: The invention relates to a process for flip-chip connection of an electronic component (D) to a substrate (B), characterized in that it comprises producing at least one interconnect pad (PC) by etching a thick conductive film and bonding it, by means of at least one conductive adhesive, between a receiving pad or area of said electronic component and a receiving pad or area (PAS) of said substrate.

公开(公告)号：EP2441088A1

公开(公告)日：2012-04-18

申请号：EP10725161.3

申请日：2010-06-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/31 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00

Abstract: The invention relates to a method for manufacturing a reconstituted wafer (100) which comprises chips (1) with bonding pads (10), said method including the following steps of manufacturing a first chip wafer (1). The method also includes the following steps: producing on said wafer a stack of at least one layer for redistributing the pads (10) of the chips on conductive tracks (12) intended for interconnecting chips, said stack being referred to as the main RDL layer (14); cutting said wafer in order to obtain individual chips (1) each with its own RDL layer (14); adding individual chips with RDL layers (14) to a substrate (20) that is rigid enough to remain flat during subsequent steps, and provided with a layer of adhesive (21), with the RDL layer (14) on the layer of adhesive (21); depositing a resin (30) in order to encapsulate the chips (1); polymerising the resin; removing the rigid substrate (20); depositing a single redistribution layer referred to as mini RDL (24) to connect the conductive tracks of the main RDL layer (14) with interconnecting contacts, via openings (22) made in the layer of adhesive (21), the wafer comprising the polymerised resin, the chips with the RDL layer thereof and the mini RDL forming the reconstituted wafer (100).

公开(公告)号：EP2406815A1

公开(公告)日：2012-01-18

申请号：EP10708971.6

申请日：2010-03-09

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/56 ,  B81C1/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/4334 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/24137 ,  H01L2224/24998 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: The invention relates to a method for producing a reconstituted board (1) that comprises chips (10) having connection pads (11) on a surface of said chip, referred to as a front surface (12), wherein the method includes the following steps: positioning the chips (10) on an adhesive substrate (20) with the front surface on the substrate, depositing a resin (50) onto the substrate (20) for encapsulating the chips, and polymerising the resin (50). Before the resin deposition step, the method includes a step of gluing a supporting plate (40) onto the chips for positioning the chips, said supporting plate (40) including portions provided on a surface (12, 13) of the chips.

公开(公告)号：EP2368262A1

公开(公告)日：2011-09-28

申请号：EP09797035.4

申请日：2009-12-18

Applicant: 3D Plus

Inventor： VAL, Christian ,  COUDERC, Pascal ,  VAL, Alexandre

IPC: H01L21/68 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/141 ,  H05K1/185 ,  H05K3/321 ,  H05K2203/1469 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/0401

Abstract: The invention relates to a method for the collective production of CMS electronic modules from a wafer (2') with metallised outputs having electronic components (22, 23, 24) moulded in the resin (28) and, on one surface, the outer outputs (26) of the electronic components on which a non-oxidisable metal or alloy (21) is deposited and a printed circuit (1) provided with pads (11) of a non-oxidisable metal or alloy. The method comprises the following steps: cutting the wafer (2') according to predetermined patterns for obtaining reconfigured moulded components (30) including at least one electronic component, assembling the reconfigured components (30) on the printed circuit (1), the metallised outer outputs of the reconfigured components being arranged opposite the metallised pads (11) of the printed circuit, and connecting, without any brazing additives, said outer outputs to the metallised pads of the printed circuit using a material (10) containing an electrically conductive ink or glue.

Abstract translation: 用于CMS电子模块的晶片级制造的工艺从具有金属化输出的晶片开始，包括以树脂模制的电子部件，以及在一侧上沉积有不可氧化的金属或合金的电子部件的外部输出，以及 设置有可氧化金属或合金接触垫的印刷电路。 在该过程中，以预定图案切割晶片以获得包括至少一个电子部件的重新配置的模制部件; 重新组装的组件被组装在印刷电路上，重新配置的组件的金属化外部输出端与印刷电路的金属化接触焊盘相对放置; 并且这些外部输出通过基于导电粘合剂或墨水的材料无焊地连接到印刷电路的金属化接触焊盘。

公开(公告)号：EP2053646B1

公开(公告)日：2010-08-18

申请号：EP08167277.6

申请日：2008-10-22

Applicant: 3D Plus

Inventor： Val, Christian

IPC: H01L25/10 ,  H01L21/98 ,  H01L23/58 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L22/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/351 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: The method involves stacking wafers (1) to superimpose zones of curved segments e.g. circle arc, of electrical connection tracks. Vias are pierced in an insulating resin along a direction of the stacking, and directly above spaces that are surrounded by the zones to form the vias. A wall of the vias is metallized by electrolytic growth. The stacking of the wafers is cut along cutting paths to form three-dimensional electronic modules, where the width of the cut of stacking is higher than the width of an electrode interconnecting the tracks.

公开(公告)号：EP2136401A1

公开(公告)日：2009-12-23

申请号：EP09172209.0

申请日：2000-12-12

Applicant: 3D Plus

Inventor： Val, Christian

IPC: H01L23/52 ,  H01L21/50 ,  H01L25/00 ,  H01L25/065 ,  H01L23/522 ,  H01L21/98

CPC classification number: H01L25/50 ,  H01L23/5222 ,  H01L24/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/184 ,  H05K1/185 ,  H05K3/045 ,  H05K3/403 ,  H05K2201/0715 ,  H05K2201/09181 ,  H05K2201/09645 ,  H05K2201/10643 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2924/00

Abstract: L'invention concerne un procédé et un dispositif d'interconnexion en trois dimensions de composants électroniques.
Pour diminuer les capacités parasites entre connexions et blindage (304) du dispositif, on découpe, dans le bloc (3') de circuits empilés dont les conducteurs (21) sont en retrait de la face correspondante (302) du bloc, des rainures (40, 41) métallisées (42), ces rainures venant entamer les conducteurs de connexion (21). L'ensemble est ensuite enrobé de résine (303) et blindé par une métallisation (304).
L'invention s'applique notamment à la réalisation de systèmes électroniques en trois dimensions à encombrement réduit.

Abstract translation: 包含电子部件和连接导体的壳体或电路的3D互连方法，其中壳体或电路通过绝缘体的封装以块（3'）的形式堆叠，包括：（a）通过离开四肢切割块 相对于相应面（302）凹入的导体（21）; （b）在面和垂直面上切割凹槽（40,41）; （c）块和槽的金属化; （d）抛光表面以去除金属化; （e）树脂包封（303）; 和（f）块的金属化以确保屏蔽（304）。 该方法还包括在本发明的一个变型中，用于向电路，母线供电，并且在步骤（b）中，至少一个沟槽切入两个相邻导体的末端; 该方法包括附加步骤，即（g）在步骤（c）和（e）之间实现的全长切割第一凹槽底部的第二凹槽。 第二槽的宽度小于第一槽的宽度。 通过锯切或使用激光来切割凹槽。 在本发明的另一变型中，该方法包括附加步骤，即（h）通过在步骤（e）之前实现的导电粘合剂将板粘合到凹槽的侧面来引入电容器。 具有三维互连的电子装置包括具有连接导体并封装以形成块体的壳体或电路，根据该方法用凹槽和金属化制成。 金属化在第二槽的全长处被中断。

公开(公告)号：EP1792526B1

公开(公告)日：2009-07-15

申请号：EP05782605.9

申请日：2005-09-07

Applicant: 3D Plus

Inventor： VAL, Christian ,  LIGNIER, Olivier ,  BOCAGE, Régis

IPC: H05K1/02 ,  H05K3/34 ,  H05K3/44 ,  H05K7/20 ,  H01L23/498 ,  H01L23/34

CPC classification number: H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0201 ,  H05K1/111 ,  H05K1/112 ,  H05K3/4641 ,  H05K2201/09718 ,  H05K2201/09745 ,  H05K2201/09781 ,  H05K2203/165 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to an electronic device provided with a heat spreader, in particular to plastic box-like devices comprising one or several stages of components. The inventive electronic device, for example a box-like, is provided with external connection pads (11) which are distributed on a connecting surface (22), comprises a heat-conductive plate (23) which is disposed in a parallel position with respect to said connecting surface and whose non-uniform structure, when the device is exposed to a given external temperature, makes it possible to carry out a controlled heat supply to each external connection pad according to the position thereof on the connecting surface. When the device is embodied in the form of a box comprising a support (20) in the form of a printed circuit, the conductive plate advantageously forms the internal layer thereof.

公开(公告)号：EP1955374A1

公开(公告)日：2008-08-13

申请号：EP06830256.1

申请日：2006-11-30

Applicant: 3D Plus

Inventor： VAL, Christian ,  LIGNIER, Olivier

IPC: H01L23/538

CPC classification number: H05K1/144 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/19041 ,  H01L2924/3512 ,  H05K1/185

Abstract: The subject of the invention is a 3D electronic module comprising a stack (100) of at least a first slice (10) and a second slice (30), the first slice (10) having on a face (101) at least one set (4) of electrically conducting bumps (41), and the second slice (30) comprising at least one zone (61) of electrically insulating material, passing through the thickness of the slice. The second slice (30) comprises at least one electrically conducting element (3) passing through the said slice in a zone (61) of electrically insulating material, capable of receiving a set (4) of bumps (41) of the first slice (10).

Abstract translation: 该模块具有两个片（10,30）的堆叠（100），其中片（10）在其表面上具有一组导电凸起。 切片（30）包括通过切片（30）的厚度的电绝缘材料区（61）和穿过该区中的切片（30）的导电元件（3）。 导电元件和凸块由具有确定的硬度的材料制成。 元件（3）的材料的硬度低于凸起材料的硬度，使得凸块穿透导电元件。