公开(公告)号：EP2400642A1

公开(公告)日：2011-12-28

申请号：EP11182534.5

申请日：2009-10-20

Applicant: STMicroelectronics Srl

Inventor： Bagarelli, Fulvio Giacomo ,  Marano, Vincenzo

IPC: H02M3/157

CPC classification number: H02M3/157 ,  H02M2001/0019 ,  H02M2003/1555

Abstract: A new and advanced PWM current control is provided by a new method and control system architecture that achieve the very high performances of an advanced current control for full-bridge stages, in terms of accuracy, error, speed and frequency response, but with an outstandingly reduced complexity in terms of analog circuits required, comparable with that of an elementary peak current control. The only analog blocks required are one current sense transducer (i.e. a series resistor or a sense-FET) and one comparator for the current sensing while the rest of the control circuitry is digital.

Abstract translation: 通过新的方法和控制系统架构提供了一个新的和先进的PWM电流控制，在精度，误差，速度和频率响应方面，实现了全桥级高级电流控制的非常高的性能，但是突出 降低了所需模拟电路的复杂性，与基本峰值电流控制相当。 所需的唯一模拟块是一个电流感测传感器（即，串联电阻或感测FET）和一个用于电流感测的比较器，而其余的控制电路是数字的。

公开(公告)号：EP1804289B1

公开(公告)日：2011-11-23

申请号：EP06026787.9

申请日：2006-12-22

Applicant: STMicroelectronics Srl

Inventor： Servalli, Giorgio ,  Capetti, Gianfranco ,  Cantú, Pietro

IPC: H01L21/8247 ,  H01L27/115 ,  G03F1/14 ,  H01L21/768

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11521

公开(公告)号：EP1845442B1

公开(公告)日：2011-11-09

申请号：EP06112507.6

申请日：2006-04-11

Applicant: STMicroelectronics Srl ,  STMicroelectronics Limited

Inventor： Bertoni, Guido Marco ,  Fragneto, Pasqualina ,  Marsh, Andrew ,  Pelosi, Gerardo ,  Ravasio, Moris

IPC: G06F7/72

CPC classification number: G06F7/728 ,  G06F7/722

公开(公告)号：EP2306503A3

公开(公告)日：2011-11-02

申请号：EP10183300.2

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device (1) is disclosed, which comprises a die (2) of semiconductor material and a support (3), the die (2) of semiconductor material including an integrated electronic circuit and a plurality of contact pads (6) associated with the electronic circuit and connected electrically to the support (3) by wire leads (4), characterized in that each contact pad of said plurality of contact pads (6) comprising a lower layer (7) of copper, or alloys thereof; and an upper layer. Advantageously, the upper layer consists of:
a first film (9) of palladium or alloys thereof, overlying the lower layer (7) of copper or alloys thereof; and optionally
a second film (10) of gold or alloys thereof, overlying the first film (9) of palladium or alloys thereof.
Moreover, the layer (7) or film (9, 10) are deposited by an electroless chemical process.

Abstract translation: 本发明公开了一种半导体电子器件（1），其包括半导体材料管芯（2）和支撑件（3），半导体材料管芯（2）包括集成电子电路和多个关联焊盘（6） 与所述电子电路并且通过引线（4）电连接到所述支撑件（3），其特征在于，所述多个接触垫（6）中的每个接触垫包括铜或其合金的下层（7）; 和上层。 有利的是，上层由以下部分组成： - 钯或其合金的第一膜（9），覆盖在铜或其合金的下层（7）上; 以及可选地覆盖钯或其合金的第一膜（9）的第二金（或其合金）膜（10）。 此外，通过无电化学处理来沉积层（7）或膜（9,10）。

公开(公告)号：EP1745505B1

公开(公告)日：2011-08-17

申请号：EP05738025.5

申请日：2005-04-18

Applicant: STMicroelectronics Srl

Inventor： PONZA, Anna ,  DEPETRO, Riccardo ,  MONTANINI, Pietro

IPC: H01L21/78

CPC classification number: H01L21/78

Abstract: A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer (5') partially suspended above a semiconductor substrate (2) and constrained to the substrate (2) by temporary anchorages (10, 15'); dividing the layer (5') into a plurality of portions (13) laterally separated from one another; and removing the temporary anchorages (10, 15'; 38), in order to free the portions (13).

公开(公告)号：EP1962054B1

公开(公告)日：2011-07-20

申请号：EP07425075.4

申请日：2007-02-13

Applicant: STMicroelectronics Srl

Inventor： Caminada, Carlo ,  Prandi, Luciano ,  Lasalandra, Ernesto

IPC: G01C19/56

CPC classification number: G01C19/5712 ,  G01C19/5726 ,  G01C19/5762

公开(公告)号：EP1320129B1

公开(公告)日：2011-07-13

申请号：EP01830768.6

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

公开(公告)号：EP2339736A1

公开(公告)日：2011-06-29

申请号：EP10197034.1

申请日：2010-12-27

Applicant: STMicroelectronics Srl

Inventor： Adragna, Claudio ,  Novelli, Aldo Vittorio ,  Santoro, Christian Leone

IPC: H02M3/337

CPC classification number: H02M3/3376 ,  Y02B70/1433

Abstract: A control device for a resonant converter is described; the converter comprises a switching circuit (Q1-Q2) adapted to drive a resonant load (Cr, 20). The resonant load comprises at least one transformer (20) with at least a primary winding (L1) and at least a secondary winding (L2) and the converter is adapted to convert an input signal (Vin) into an output signal (Vout); the switching circuit comprises at least a half bridge of first (Q1) and second (Q2) switches and the central point (HB) of said half bridge is connected to said resonant load (Cr, 20). The control device comprises first means (116) adapted to rectify a signal (Vs) representative of the current (Ir) circulating in the primary winding, second means (111) adapted to integrate at least said rectified signal (Vs') and being adapted to generate at least a control signal (HSGD, LSGD) of said switching circuit according to the integrated signal (Vint), third means (FF, CO1, 118, CO2) adapted to send a reset command to said second means so as to inhibit the operation over a time period (Tres) between the instant when said integrated signal reaches or overcomes a first signal (Vc, V2) and the instant of the next zero crossing of the signal (Vs) representative of the current (Ir) circulating in the primary winding. ( Figure 3 )

Abstract translation: 描述了用于谐振转换器的控制装置; 该转换器包括适于驱动谐振负载（Cr，20）的开关电路（Q1-Q2）。 所述谐振负载包括具有至少一个初级绕组（L1）和至少一个次级绕组（L2）的至少一个变压器（20），并且所述转换器适于将输入信号（Vin）转换成输出信号（Vout）; 开关电路至少包括第一（Q1）和第二（Q2）开关的半桥，并且所述半桥的中心点（HB）连接到所述谐振负载（Cr，20）。 控制装置包括适于对表示在初级绕组中循环的电流（Ir）的信号（Vs）进行整流的第一装置（116），适用于至少整合所述整流信号（Vs'）并且被适配的第二装置（111） 以根据积分信号（Vint）产生所述开关电路的至少一个控制信号（HSGD，LSGD）;第三装置（FF，CO1,118，CO2），适于向所述第二装置发送复位命令以便禁止 在所述积分信号达到或克服第一信号（Vc，V2）的瞬间与代表电流（Ir）的信号（Vs）的下一个过零点之间的时间段（Tres） 初级绕组。 （图3）

公开(公告)号：EP2339735A1

公开(公告)日：2011-06-29

申请号：EP10197026.7

申请日：2010-12-27

Applicant: STMicroelectronics Srl

Inventor： Adradna, Claudio

IPC: H02M3/337

CPC classification number: H02M3/3376 ,  Y02B70/1433

Abstract: There is described an integrated circuit (103) for an oscillator (101) adapted to drive a control device (100) of a switching resonant converter; the converter comprises a switching circuit (Q1-Q2) adapted to drive a resonant load (Cr, 20) provided with at least one transformer (20) with at least a primary winding (L1) and at least a secondary winding (L2). The control device is adapted to drive the switching circuit and the converter is adapted to convert an input signal (Vin) into an output signal (Vout). The integrated circuit comprises first means (Q20, Q3-Q7, 113-115) adapted to charge and discharge a capacitor (Ct) by a first current signal (Ic + i p (t)) such that the voltage (Vct) at the terminals of said capacitor is between first (Vv) and second (Vp) reference voltages, with said second reference voltage higher than said first reference voltage. The current signal (Ic + i p (t)) comprises a second current signal (Ic) representative of the feedback loop that controls the output signal (Vout) of the converter; the integrated circuit comprises second means (110) adapted to rectify a signal (Vs) representative of the current (Ir) circulating in the primary winding (L1) and the first current signal (Ic + i p (t)) comprises a third current signal (i p (t)) proportional to the rectified signal. ( Figure 3 )

Abstract translation: 中，描述了在用于在振荡器（101）angepasst到驱动开关谐振变换器的控制设备（100）的集成电路（103）; 该转换器包括一个开关电路（Q1-Q2）angepasst驱动谐振负载（CR，20）设置有至少一个变压器（20），具有至少一个初级绕组（L1）和至少一个次级绕组（L2）。 该控制装置是angepasst来驱动开关电路和转换器是angepasst对输入信号（Vin）转换为在输出端信号（Vout）。 第一集成电路包括装置（Q20，Q3-Q7，113-115）angepasst充电和由第一电流信号放电的电容器（CT）（IC + IP（t））的检查在端子做的电压（VCT） 说的电容器是第一（VV）和第二（VP）的参考电压之间，其中所述第二参考电压高于所述第一参考电压高。 电流信号（IC + I P（t））的包含第二电流信号（Ic）的代表的反馈环路的那样控制输出信号（Vout）的转换器的; 该集成电路包括第二装置（110）angepasst纠正信号（Vs）代表的电流（Ir）的的在初级绕组（L1）和所述第一电流信号（Ic的+ IP（t））的循环包括第三电流信号 （IP（t））的成比例的整流信号。 （图3）

公开(公告)号：EP2339637A1

公开(公告)日：2011-06-29

申请号：EP10197215.6

申请日：2010-12-28

Applicant: STMicroelectronics Srl

Inventor： Micciché, Monica ,  Grimaldi, Antonio Giuseppe ,  Adragna, Claudio

IPC: H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H02M3/335

CPC classification number: H01L29/7816 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66681 ,  H02M3/33592 ,  Y02B70/1475

Abstract: An integrated power MOSFET device formed by a substrate (19, 65); an epitaxial layer (13; 68; 80, 81) of N type ; a sinker region (17b) of P type, extending through the epitaxial layer from the top surface and in electrical contact with the substrate; a body region (22), of P type, extending within the sinker region from the top surface; a source region (25), of N type, extending within the body region from the top surface, the source region delimiting a channel region (22a); a gate region (19); a source contact (30), electrically connected to the body region and to the source region; a drain contact (31), electrically connected to the epitaxial layer (13; 81); and a source metallization region (104), extending over the rear surface and electrically connected to the substrate and to the sinker region.

Abstract translation: 由衬底（19,65）形成的集成功率MOSFET器件; N型外延层（13; 68; 80,81）; P型沉降片区域（17b），从顶表面延伸穿过外延层并与衬底电接触; P型的主体区域（22），从所述顶表面延伸到所述沉降片区域内; 源区域（25），其从所述顶表面在所述体区域内延伸，所述源区域限定沟道区域（22a）; 栅极区域（19）; 源极触点（30），电连接到所述主体区域和所述源极区域; 电连接到外延层（13; 81）的漏极接触（31）; 以及源极金属化区域（104），其在所述后表面上延伸并且电连接到所述衬底和所述沉降弧区域。