公开(公告)号：WO1998028749A1

公开(公告)日：1998-07-02

申请号：PCT/US1997010082

申请日：1997-06-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  VAN BUSKIRK, Michael

IPC: G11C16/06

CPC classification number: G11C8/16 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/22

Abstract: A non-volatile memory having a non-volatile memory array arranged as a plurality of sectors each containing an array of non-volatile memory cells. The non-volatile memory includes independent read and write paths and selection circuitry for each sector that enables a read operation from one of the sectors during a program or erase operation to one of the other sectors.

Abstract translation: 一种非易失性存储器，其具有排列成多个扇区的非易失性存储器阵列，每个扇区都包含非易失性存储单元阵列。 非易失性存储器包括用于每个扇区的独立的读取和写入路径和选择电路，其能够在对其他扇区之一进行编程或擦除操作期间从扇区中的一个读取操作。

公开(公告)号：WO1998025182A1

公开(公告)日：1998-06-11

申请号：PCT/US1997022616

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F07/20

CPC classification number: G03F7/70433 ,  G03F1/70 ,  G03F7/70241

Abstract: A reticle (130) provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions (132, 134) for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.

Abstract translation: 掩模版（130）提供图像图案并补偿光刻系统中的透镜误差。 使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。 通过调节辐射透射区域（132,134）的配置（或布局），例如通过调节石英基底的顶表面上的铬图案，可以对掩模版进行结构上的修改。 或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。 图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

公开(公告)号：WO1998024120A1

公开(公告)日：1998-06-04

申请号：PCT/US1997010757

申请日：1997-06-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  IBOK, Effiong, E.

IPC: H01L21/316

CPC classification number: H01L21/02164 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/31662 ,  H01L29/42364 ,  H01L29/518 ,  Y10S438/966

Abstract: A method of manufacturing a semiconductor device to negate the effects on the device performance caused by defects on the silicon substrate. An oxygen-doped amorphous silicon layer is deposited onto the gate region of the semiconductor device and can have a thickness of less than 5 nanometers. The amorphous silicon provides a conformal layer over the defects on the silicon substrate. The oxygen doping of the amorphous silicon maintains the conformality of the amorphous silicon layer during subsequent processing by preventing the formation of large amorphous silicon grains during a crystallization process. The resulting silicon oxide layer has increased uniformity and can have a thickness of less than 10 nanometers.

Abstract translation: 一种制造半导体器件以消除由硅衬底上的缺陷引起的对器件性能的影响的方法。 氧掺杂非晶硅层沉积在半导体器件的栅极区上，并且可以具有小于5纳米的厚度。 非晶硅在硅衬底上的缺陷上提供共形层。 非晶硅的氧掺杂通过防止在结晶过程中形成大的非晶硅晶粒而在随后的加工过程中保持非晶硅层的共形性。 所得到的氧化硅层具有增加的均匀性，并且可以具有小于10纳米的厚度。

公开(公告)号：WO1998023036A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021367

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  SCHNIZLEIN, Paul ,  BELL, Ed

IPC: H03L07/14

CPC classification number: H04L27/22 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/146 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/2273 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers start to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time. By thus anticipating the frequency of the carrier, this carrier-recovery loop can have an improved acquisition time to reach phase lock. The initialization value of the feedback signal can be generated by recording a sample of the feedback signal when the carrier-recovery loop is phase-locked to a received signal or to an on-board crystal oscillator. The invention also includes a mechanism to correct drifts in the crystal oscillator's frequency.

Abstract translation: 具有促进循环初始化的特征的通信系统中的接收机的载波恢复回路。 载波恢复环路是使用反馈信号将恢复振荡器锁相到接收信号的载波的PLL。 在本发明中，将反馈信号的初始化值存储在存储器中并提供给数字控制的恢复振荡器（DCO）。 该初始化值使恢复的信号达到近似载波频率的初始频率。 当接收机开始与载波获取锁相时，载波恢复环路处于接近期望相位锁的状态。 以这种方式准备DCO对载体恢复循环有显着的改进。 环路获取锁相的响应时间部分取决于其与载波的初始频率偏移。 一般来说，减少初始偏移可以减少环路的采集时间。 通过这样预期载波的频率，该载波恢复回路可以具有改善的采集时间以达到锁相。 反馈信号的初始化值可以通过当载波恢复回路被锁相到接收信号时记录反馈信号的样本，或通过记录在板上的晶体振荡器来产生。 本发明还包括校正晶体振荡器频率漂移的机制。

公开(公告)号：WO1998020420A1

公开(公告)日：1998-05-14

申请号：PCT/US1996017517

申请日：1996-11-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WITT, David, B. ,  HATTANGADI, Rajiv, M.

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  G06F9/30152 ,  G06F9/3824 ,  G06F9/3832 ,  G06F12/0855 ,  G06F12/0864 ,  G06F2212/6082

Abstract: A data cache configured to perform store accesses in a single clock cycle is provided. The data cache speculatively stores data within a predicted way of the cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete. If the way prediction is incorrect, then the captured data is restored to the predicted way. If the store access hits in an unpredicted way, the store data is transferred into the correct storage location within the data cache concurrently with the restoration of data in the predicted storage location. Each store for which the way prediction is correct utilizes a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output. Therefore, the access time of the associative data cache may be substantially similar to a direct-mapped cache access time. The present data cache is therefore suitable for high frequency superscalar microprocessors.

Abstract translation: 提供了被配置为在单个时钟周期中执行存储访问的数据高速缓存。 在以预测的方式捕获当前存储的数据之后，数据高速缓存以推测性方式将数据存储在高速缓存的预测方式中。 在随后的时钟周期中，用于存储访问的高速缓存命中信息验证预测方式。 如果预测方式正确，那么商店是完整的。 如果预测方式不正确，则捕获的数据将恢复到预测的方式。 如果存储访问以不可预测的方式命中，则将存储数据与恢复预测存储位置中的数据同时传送到数据高速缓存内的正确存储位置。 预测方式正确的每个商店利用数据高速缓存带宽的单个时钟周期。 此外，在数据高速缓存中实现的预测结构的方式绕过数据高速缓存的标签比较，以选择输出的数据字节。 因此，关联数据高速缓存的访问时间可以基本上类似于直接映射的高速缓存访​​问时间。 因此，本数据高速缓存适用于高频超标量微处理器。

公开(公告)号：WO1998013933A1

公开(公告)日：1998-04-02

申请号：PCT/US1997017149

申请日：1997-09-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GAGLANI, Parnay

IPC: H03H17/06

CPC classification number: H03H17/0664

Abstract: A decimation device has a sampler, a memory and an adder in the decimation stage. The sampler and the adder form a partial sample for storage in the memory at a sample time. At a next sample time the sum of a current sample and the partial sample is output from the decimation stage. The partial sample is formed by adding the first sample to a value equal to twice a second sample obtained after the first sample.

Abstract translation: 抽取装置在抽取级中具有采样器，存储器和加法器。 采样器和加法器形成部分样本，用于在采样时间存储在存储器中。 在下一个采样时间，从抽取级输出当前采样和部分采样的和。 通过将第一样品添加到等于第一样品之后获得的第二样品的两倍的值来形成部分样品。

公开(公告)号：WO1998013767A1

公开(公告)日：1998-04-02

申请号：PCT/US1997017197

申请日：1997-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GULICK, Dale

IPC: G06F13/40

CPC classification number: G06F13/122 ,  G06F13/4059

Abstract: The present invention discloses a system and method for communicating real-time, multimedia data between a host CPU and an external multimedia device using a pair of first-in-first-out (FIFO) buffers. Data from the CPU is stored in a first FIFO buffer and subsequently retrieved by the multimedia device. Data from the multimedia device is stored in a second FIFO buffer and subsequently retrieved by the CPU for processing. The FIFO buffers provide indications to the CPU for the CPU to store more data in the first FIFO buffer and for the CPU to retrieve data from the second FIFO buffer.

Abstract translation: 本发明公开了一种使用一对先进先出（FIFO）缓冲器在主机CPU和外部多媒体设备之间传送实时多媒体数据的系统和方法。 来自CPU的数据被存储在第一FIFO缓冲器中，随后由多媒体设备检索。 来自多媒体设备的数据被存储在第二FIFO缓冲器中，随后由CPU检索以进行处理。 FIFO缓冲器向CPU提供指示，以便CPU将更多数据存储在第一FIFO缓冲器中，并且CPU从第二FIFO缓冲器中检索数据。

公开(公告)号：WO1998010527A1

公开(公告)日：1998-03-12

申请号：PCT/US1997006092

申请日：1997-04-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHENG, Yi

IPC: H04B03/14

CPC classification number: H03H11/0422 ,  H04B3/144

Abstract: A CMOS transmission line equalizer is provided for receiving distorted signals transmitted through a transmission line and for compensating for the signal distortion. The equalizer has a transfer function characteristic with a single pole and a single zero. The transfer function includes a mirroring ratio circuit (CMR) for controlling the ratio between the single pole and the single zero. The mirroring ratio circuit is controlled by transistor size ratio. The single zero serves to cancel the dominant pole in the transfer function of the transmission line so as to compensate for the signal distortion caused by the transmission line.

Abstract translation: 提供CMOS传输线均衡器用于接收通过传输线传输的失真信号并补偿信号失真。 均衡器具有单极和单个零的传递函数特性。 传递函数包括用于控制单极和单个零之间的比率的镜像比电路（CMR）。 镜像比电路由晶体管尺寸比控制。 单个零用于消除传输线的传递函数中的主极，以补偿由传输线引起的信号失真。

公开(公告)号：WO1998009318A1

公开(公告)日：1998-03-05

申请号：PCT/US1997005133

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  PRAMANICK, Shekhar ,  SINGH, Bhanwar ,  NG, Che-Hoo

IPC: H01L21/027

CPC classification number: H01L21/76886 ,  H01L21/0276 ,  H01L21/76888 ,  Y10S438/952

Abstract: The application of a dissimilar anti-reflective coating on a conductive layer during photolithographic processing is avoided, as by modifying a portion of the upper surface (21A) of the conductive layer (21) to exhibit anti-reflective properties. In an embodiment of the present invention, impurity ions are implanted into a portion of the upper surface (21A) of an aluminum or an aluminum-alloy conductive layer (21) to render the upper portion (21A) substantially amorphous and, hence, decrease its reflectivity to perform an anti-reflective function.

Abstract translation: 通过改变导电层（21）的上表面（21A）的一部分以显示抗反射性能，避免了在光刻处理期间在导电层上施加不同的抗反射涂层。 在本发明的一个实施例中，杂质离子注入到铝或铝合金导电层（21）的上表面（21A）的一部分中，以使上部（21A）基本上是无定形的，因此减小 其反射性可以进行抗反射功能。

公开(公告)号：WO1998008324A2

公开(公告)日：1998-02-26

申请号：PCT/US1997014480

申请日：1997-08-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  DETTMER, David, R.

IPC: H04L05/00

CPC classification number: H03G3/3026 ,  H03G3/001

Abstract: A near full duplex portable handset speakerphone comprises: a microprocessor; a hands-free receiver register connected to the microprocessor; a hands-free transmit register connected to the microprocessor; a ROM having a speakerphone operation algorithm, the ROM connected to the microprocessor; a first analog-to-digital converter connected to the hands-free receiver register; a second analog-to-digital converter connected to the hands-free transmit register; a first programmable digital attenuator connected to the microprocessor and to a speaker; and a second programmable digital attenuator connected to the microprocessor and to a microphone, wherein near full duplex communication is achieved without digital signal processing. In another feature of the invention, the hands-free registers provide a digital representation of the speech volume in each direction to the microprocessor. The microprocessor monitors the speech signal levels, calculates digital volume comparisons in order to make speech gain decisions for optimal sound, and digitally adjusts the gains in the two speech paths to the upper half of their maximum values.

Abstract translation: 近全双工便携式手持扬声器包括：微处理器; 连接到微处理器的免提接收器寄存器; 连接到微处理器的免提传输寄存器; 具有扬声器操作算法的ROM，连接到微处理器的ROM; 连接到免提接收机寄存器的第一模数转换器; 连接到免提发送寄存器的第二模数转换器; 连接到微处理器和扬声器的第一可编程数字衰减器; 以及连接到微处理器和麦克风的第二可编程数字衰减器，其中在没有数字信号处理的情况下实现近全双工通信。 在本发明的另一特征中，免提寄存器在每个方向向微处理器提供语音音量的数字表示。 微处理器监视语音信号电平，计算数字音量比较，以便为最佳声音做出语音增益决策，并将两个语音路径中的增益数字调整到其最大值的上半部分。