公开(公告)号：DE69419723D1

公开(公告)日：1999-09-02

申请号：DE69419723

申请日：1994-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C17/00

公开(公告)号：DE69226400D1

公开(公告)日：1998-09-03

申请号：DE69226400

申请日：1992-05-05

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C11/409 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28 ,  G11C16/30 ,  G11C17/00 ,  G11C17/18

Abstract: A modulated-current offset-type or currentunbalance, offset-type sense amplifier for reading programmable memory cells employs loads identical to each other and a differential input pair of transistors of the differential amplifier are "cross-coupled" with said identical loads to realize a latch structure for storing an extracted data. The circuit utilizes three timing signals for sequentially modifying the configuration of the circuit and defining the following phases: start of a new reading cycle, pre-charging of capacitances associated with bit lines, and equalization of output nodes and line potentials, discrimination phase, reading and storing of the extracted data. Different embodiments employing different reference systems are described.

公开(公告)号：DE69222249T2

公开(公告)日：1998-04-02

申请号：DE69222249

申请日：1992-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

IPC: G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C7/00 ,  G11C5/06

Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by implifying the sensing process.

公开(公告)号：DE69224125D1

公开(公告)日：1998-02-26

申请号：DE69224125

申请日：1992-09-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C7/14 ,  G11C16/28 ,  G11C7/00 ,  G11C16/06

公开(公告)号：IT1253684B

公开(公告)日：1995-08-22

申请号：ITVA910034

申请日：1991-09-26

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C20060101 ,  G11C

Abstract: A dynamic reference system for sense-amplifier is realised by utilising the dual signals generated at the respective output nodes of the two cascode circuits normally used to control the switches connecting the loads to the respective lines, in order to further control two imbalance transistors functionally connected between the switches and a source of polarisation current and essentially having different dimensions from each other, in order to superimpose an offset current on the current forced across the loads of the two lines of the input network so as to enable a discrimination even in the event of identical selected locations. The reference system is simple to construct and offers numerous advantages with respect to the static reference systems of the prior art.

公开(公告)号：IT1249809B

公开(公告)日：1995-03-28

申请号：ITVA910012

申请日：1991-05-10

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C11/409 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28 ,  G11C16/30 ,  G11C17/00 ,  G11C17/18 ,  H03K

Abstract: A modulated-current offset-type or currentunbalance, offset-type sense amplifier for reading programmable memory cells employs loads identical to each other and a differential input pair of transistors of the differential amplifier are "cross-coupled" with said identical loads to realize a latch structure for storing an extracted data. The circuit utilizes three timing signals for sequentially modifying the configuration of the circuit and defining the following phases: start of a new reading cycle, pre-charging of capacitances associated with bit lines, and equalization of output nodes and line potentials, discrimination phase, reading and storing of the extracted data. Different embodiments employing different reference systems are described.

公开(公告)号：ITVA910027D0

公开(公告)日：1991-08-30

申请号：ITVA910027

申请日：1991-08-30

Applicant: ST MICROELECTRONICS SRL ,  SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI

IPC: G11C17/18 ,  G11C8/10 ,  G11C17/12

Abstract: A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection means driven through five buses for implementing a two-level decoding, thus driving a fractionary number of rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.