公开(公告)号：EP2120520A2

公开(公告)日：2009-11-18

申请号：EP09000433.4

申请日：2009-01-14

Applicant: LG Electronics Inc.

Inventor： Yum, Jungsup ,  Ko, Dongki

IPC: H05K3/24 ,  H05K1/14 ,  H05K3/42

CPC classification number: H05K3/181 ,  H05K1/0393 ,  H05K3/422 ,  H05K3/426 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/09827 ,  Y10T428/12375 ,  Y10T428/12396 ,  Y10T428/12472 ,  Y10T428/12493 ,  Y10T428/12569 ,  Y10T428/12771 ,  Y10T428/12847 ,  Y10T428/12889 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/12944

Abstract: A flexible film (100) and a display device including the same are disclosed. The flexible film includes an insulating film (110) including at least one hole (120). The insulating film further includes a first surface (111a) corresponding to an inner circumferential surface of the hole, a second surface (111b) corresponding to an upper surface of the insulating film, and a third surface (111c) corresponding to a lower surface of the insulating film. The flexible film includes a first metal layer (131) and a second metal layer (132) that is positioned on the first surface and at least one of the second and third surfaces. A thickness (T1) of the first metal layer is smaller than a thickness (T2) of the second metal layer.

Abstract translation: 公开了一种柔性膜（100）和包括该柔性膜的显示装置。 柔性膜包括包括至少一个孔（120）的绝缘膜（110）。 所述绝缘膜还包括与所述孔的内周面相对应的第一面（111a），对应于所述绝缘膜的上表面的第二面（111b）和与所述绝缘膜的下表面对应的第三面（111c） 绝缘膜。 柔性膜包括位于第一表面和第二表面和第三表面中的至少一个表面上的第一金属层（131）和第二金属层（132）。 第一金属层的厚度（T1）小于第二金属层的厚度（T2）。

公开(公告)号：EP1919266A3

公开(公告)日：2009-08-05

申请号：EP08150255.1

申请日：1999-09-14

Applicant: Ibiden Co., Ltd.

Inventor： En, Honchin ,  Nakai, Tohru ,  Oki, Takeo ,  Hirose, Naohiro ,  Noda, Kouta

IPC: H05K3/18 ,  H05K3/46 ,  H05K1/09 ,  C25D5/18 ,  C23C18/34

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An electroless plating solution comprises an aqueous solution containing 0.025 to 0.25 mol/L of a basic compound, 0.03 to 0.15 mol/L of a reducing agent, 0.02 to 0.06 mol/L of copper ion and 0.05 to 0.3 mol/L of tartaric acid or a salt thereof. Another electroless plating solution comprises an aqueous solution containing a basic compound, a reducing agent, copper ion, tartaric acid or a salt thereof and at least one metal ion species selected from the group consisting of nickel ion, cobalt ion and iron ion. The electroless plating solution is used in an electroless plating process performing electroless copper plating, more specifically in a process for manufacturing a printed circuit board which comprises immersing a resin insulating substrate board in the electroless plating solution. The electroless plated film has a stress of 0 to +10 kg/mm 2 when formed on a roughened surface of the resin insulating substrate board.

公开(公告)号：EP1667504A1

公开(公告)日：2006-06-07

申请号：EP06003704.1

申请日：1999-09-14

Applicant: IBIDEN CO., LTD.

Inventor： En, Honchin ,  Nakai, Tohru ,  Oki, Takeo ,  Hirose, Naohiro ,  Noda, Kouta

IPC: H05K3/18 ,  H05K3/46 ,  H05K1/09 ,  C25D5/18 ,  C23C18/34

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: There is provided a process for manufacturing a multilayer printed circuit board which comprises at least: a step for thinning the copper foil of a copper-clad laminate by etching; a step for pattern-etching the copper foil of the copper-clad laminate to construct a conductor circuit; and a step for serially building up an interlayer resin insulating layer and a conductor layer alternately over the conductor circuit. The process may further comprise steps for producing plated through holes. The thickness of the conductor circuit may be controlled so as to be not greater by more than 10 µm than the thickness of the conductor layer on the interlayer resin insulating layer. The multilayer printed circuit board comprises a core board having a conductor circuit and, as built over the conductor circuit, a buildup wiring layer obtainable by building up the interlayer resin insulating layer and the conductor layer alternately with the conductor layers being interconnected by via holes.

Abstract translation: 提供了一种制造多层印刷电路板的方法，该方法至少包括：通过蚀刻来稀薄覆铜层压板的铜箔的步骤; 用于图案蚀刻覆铜层压板的铜箔以构造导体电路的步骤; 以及在导体电路上交替地串联建立层间树脂绝缘层和导体层的步骤。 该方法还可以包括用于生产电镀通孔的步骤。 可以将导体电路的厚度控制为不超过层间树脂绝缘层上的导体层的厚度大于10μm。 所述多层印刷电路板包括具有导体电路的芯板，并且在所述导体电路上形成的叠层布线层可通过与所述导体层互相连接而形成层叠树脂绝缘层和所述导体层而形成的叠层布线层。

公开(公告)号：EP1360720A2

公开(公告)日：2003-11-12

申请号：EP02702009.8

申请日：2002-01-15

Applicant: MacDermid, Incorporated

Inventor： KUKANSKIS, Peter ,  FRITZ, Dennis ,  DURSO, Frank ,  CASTALDI, Steven ,  SAWOSKA, David

IPC: H01L23/48 ,  C23F1/00 ,  B44C1/22

CPC classification number: H01C17/24 ,  H01C17/242 ,  H05K1/167 ,  H05K3/027 ,  H05K3/064 ,  H05K3/184 ,  H05K2201/0344 ,  H05K2203/0315 ,  H05K2203/107 ,  H05K2203/1105 ,  H05K2203/1453 ,  H05K2203/171

Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.

Abstract translation: 通过将电阻器电镀到绝缘衬底上，可以看出电阻器可以与印刷电路板一体制造的过程。 作为改善镀敷电阻器的均匀性和一致性的技术，讨论了通过蚀刻和电镀电阻器的氧化来使绝缘基板均匀化。 修剪和烘烤也被公开为调整和稳定电镀电阻器的电阻的方法。

公开(公告)号：EP0624054B1

公开(公告)日：1997-11-05

申请号：EP94107157.3

申请日：1994-05-06

Applicant: IBIDEN CO, LTD.

Inventor： Tamaki, Masanori, c/o Ibiden Co.,Ltd.

IPC: H05K3/38 ,  H05K1/09

CPC classification number: H05K3/38 ,  H05K1/09 ,  H05K3/181 ,  H05K2201/0344 ,  H05K2201/2072 ,  Y10S428/901 ,  Y10T428/12687 ,  Y10T428/12868 ,  Y10T428/12882 ,  Y10T428/12937 ,  Y10T428/24917 ,  Y10T428/249994 ,  Y10T428/25 ,  Y10T428/254

公开(公告)号：EP0738456A1

公开(公告)日：1996-10-23

申请号：EP95935814.0

申请日：1995-10-27

Applicant: Blaupunkt-Werke GmbH

Inventor： BACKASCH, Wolf ,  HOHMANN, Rolf

IPC: H05K3

CPC classification number: H05K3/244 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K3/428 ,  H05K2201/0344 ,  H05K2203/0571 ,  H05K2203/1423 ,  Y10T29/49165

Abstract: The invention proposes a method of producing a feedthrough on a circuit board, the method calling for the circuit board first to be drilled, catalysed and the surface structured. The feedthrough is then built up by electro-deposition in such a way that electrical components can be mounted in the feedthrough. The metallization (7) is preferably carried out using nickel or nickel compounds so that no additional corrosion-protection measures are necessary. By coating connecting lands (2b) with gold or palladium, bonding can be carried out directly on the lands.

公开(公告)号：EP0645074A1

公开(公告)日：1995-03-29

申请号：EP93913258.0

申请日：1993-06-01

Applicant: KNOPP, John Frederick David

Inventor： KNOPP, John Frederick David

IPC: H05K3

CPC classification number: H05K3/428 ,  H05K2201/0344 ,  H05K2203/0565 ,  H05K2203/0723 ,  H05K2203/1383

Abstract: A method of making a plate through hole printed circuit board, comprises the steps of: a) forming conductive circuit elements (20) on two opposed faces of a non-conductive substrate (21); b) coating the substrate and circuit elements with a de-sensitising material (22); c) forming holes (23) through the substrate, each hole passing through a circuit element on each of the opposed faces of the board; d) treating the board to render the substrate exposed in the holes receptive to the action of a metallic plating solution; e) removing the de-sensitising material; and f) treating the board with a metallic plating solution to deposit conductive metal (24) in the holes to the desired thickness to provide an electrical connection through each hole between two opposed conductive circuit elements. This may be in two stages, with an initial thin layer of copper being deposited, followed by a main layer of nickel to the desired thickness.

公开(公告)号：EP0435717B1

公开(公告)日：1994-08-31

申请号：EP90403493.1

申请日：1990-12-07

Applicant: BULL S.A.

Inventor： Chantraine, Philippe ,  Zorrilla, Marta

IPC: H05K3/42

CPC classification number: H05K3/422 ,  H05K3/0055 ,  H05K3/4644 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09563 ,  H05K2203/095

公开(公告)号：EP0559384A3

公开(公告)日：1993-10-20

申请号：EP93301437.5

申请日：1993-02-25

Applicant: AT&T Corp.

Inventor： Fuchs, Harold E.

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H05K1/0393 ,  H05K1/112 ,  H05K3/0032 ,  H05K3/243 ,  H05K3/426 ,  H05K2201/0154 ,  H05K2201/0344 ,  H05K2201/10674 ,  H05K2203/0455

Abstract: Disclosed is a method for fabricating devices, and the resulting products, using Tape Automated Bonding (TAB) technology. Via holes (30) are formed through a flexible insulating layer (11), such as polyimide, and are plated through when conductive fingers (12) are formed on one surface of the layer. The resulting structure is then bonded to a semiconductor chip (41) by means of the conductive pads (20) formed on the surface of the insulating layer opposite to the conductive fingers.

公开(公告)号：EP0324189A3

公开(公告)日：1990-03-07

申请号：EP88121921.6

申请日：1988-12-31

Applicant: BAYER AG

Inventor： Wolf, Gerhard Dieter, Dr. ,  Sirinyan, Kirkor, Dr. ,  von Gizycki, Ulrich, Dr. ,  Merten, Rudolf, Dr. ,  Langer, Friedrich

IPC: H05K3/38 ,  H05K3/18

CPC classification number: C23C2/02 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/426 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1152 ,  Y10T29/49165

Abstract: Leiterplatten mit gut haftenden Leiterbahnen erhält man, wenn man die Basisplatten, die beidseitig mit Kupfer­folien kaschiert sind, chemisch oder mechanisch von dieser Kaschierung befreit, aktiviert, gegebenenfalls sensibilisiert, in einem stromlosen Metallisierungsbad mit einer 0,05 -2,0 µm starken Schicht aus Nickel, Kobalt, Mangan, einem Nickel/Eisen-oder Nickel/ Kobalt-­Gemisch versieht, in einem darauffolgenden Kupferbad eine 0,5-5,0 µm dicke Kupferschicht aufbringt und darauf nach üblichen Semiadditivmethoden das Leiterbild aufbaut.