公开(公告)号：US07683393B2

公开(公告)日：2010-03-23

申请号：US11294539

申请日：2005-12-06

Applicant: Makoto Nagai ,  Setsuo Yada ,  Atsushi Uchida

Inventor： Makoto Nagai ,  Setsuo Yada ,  Atsushi Uchida

IPC: H01L27/15 ,  H01L33/00

CPC classification number: H05K1/183 ,  H01L33/486 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/32225 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/246 ,  H05K3/4614 ,  H05K3/4629 ,  H05K3/4697 ,  H05K2201/0347 ,  H05K2201/09836 ,  H05K2201/09981 ,  H05K2201/10106 ,  H05K2203/061

Abstract: A wiring substrate for mounting a light emitting element, comprising: a substrate body comprising an insulating material and having a first surface and a back surface; and a cavity being opened into the first surface of said substrate body and having a mounting area for mounting a light emitting element at a bottom face of said cavity, wherein a metalized layer provided along a side face of said cavity and metalized layers provided in said substrate body are provided to continue to each other.

Abstract translation: 一种用于安装发光元件的布线基板，包括：基板主体，包括绝缘材料并具有第一表面和后表面; 并且一个空腔被打开到所述基片主体的第一表面中，并且具有用于将发光元件安装在所述空腔的底面的安装区域，其中沿着所述空腔的侧面设置的金属化层和设置在所述腔中的金属化层 衬底本体被设置成彼此连续。

公开(公告)号：US20090279274A1

公开(公告)日：2009-11-12

申请号：US11794652

申请日：2005-12-22

Applicant: Martin Joseph Agnew ,  Gary David Panaghiston ,  Murray Jerel Niman ,  Nicholas Chandler

Inventor： Martin Joseph Agnew ,  Gary David Panaghiston ,  Murray Jerel Niman ,  Nicholas Chandler

IPC: H05K1/11

CPC classification number: H05K1/0218 ,  H05K1/142 ,  H05K1/144 ,  H05K1/145 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/0397 ,  H05K2201/0715 ,  H05K2201/0919 ,  H05K2201/09836

Abstract: The invention relates to circuit boards and to screening circuits and components on such boards from stray rf interference when they are mounted as arrays or stacks of such circuit boards. The circuit boards (12, 14) are individually screened by conductive screening layers (16, 18) as known in the art and the individual screening layers are coupled together by layered interconnects (34) which connect corresponding screening layers (16, 18) of the individual circuit boards (12, 14) together, instead of by vias.

Abstract translation: 本发明涉及电路板，并且当这些电路板被安装为这种电路板的阵列或叠层时，将这些电路板上的电路和组件从杂散干扰中筛选出来。 电路板（12,14）由本领域已知的导电屏蔽层（16,18）单独地屏蔽，并且各个屏蔽层通过分层互连（34）耦合在一起，分层互连（34）将相应的屏蔽层（16,18） 各个电路板（12,14）组合在一起，而不是通孔。

公开(公告)号：US20090008144A1

公开(公告)日：2009-01-08

申请号：US12211529

申请日：2008-09-16

Applicant: Chin Hui Chong ,  Choon Kuan Lee

Inventor： Chin Hui Chong ,  Choon Kuan Lee

IPC: H05K1/11

CPC classification number: H01R12/526 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09836 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/4922

Abstract: Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting electronic components includes a dielectric portion having a first surface and a second surface. A first terminal is disposed on the first surface of the dielectric portion for connection to a first electronic component. A second terminal is disposed on the second surface of the dielectric portion for connection to a second electronic component. The apparatus further includes a passage extending through the dielectric portion along a longitudinal axis oriented at an oblique angle relative to the first surface. The passage is at least partially filled with conductive material electrically connecting the first terminal to the second terminal.

Abstract translation: 本文公开了具有倾斜通孔的电路板，微电子器件和其它设备。 在一个实施例中，用于互连电子部件的装置包括具有第一表面和第二表面的电介质部分。 第一端子设置在电介质部分的第一表面上，用于连接到第一电子部件。 第二端子设置在电介质部分的第二表面上，用于连接到第二电子部件。 该装置还包括沿着相对于第一表面以倾斜角定向的纵向轴线延伸通过电介质部分的通道。 该通道至少部分地填充有将第一端子与第二端子电连接的导电材料。

公开(公告)号：US07274105B2

公开(公告)日：2007-09-25

申请号：US11287834

申请日：2005-11-28

Applicant: M. Ray Fairchild ,  Aleksandra Djordjevic ,  Javier Ruiz

Inventor： M. Ray Fairchild ,  Aleksandra Djordjevic ,  Javier Ruiz

IPC: H01L23/48 ,  H01L23/498 ,  H05K1/02 ,  H05K3/34 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H01L23/3677 ,  H01L24/33 ,  H01L2224/32225 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H05K3/0061 ,  H05K2201/09836 ,  H01L2924/00

Abstract: An electronics assembly is provided including a circuit board substrate having a top surface and a bottom surface and a plurality of thermal conductive vias extending from the top surface to the bottom surface. At least one electronics package is mounted to the top surface of the substrate. A heat sink device is in thermal communication with the bottom surface of the substrate. Thermal conductive vias are in thermal communication to pass thermal energy from the at least one electronics package to the heat sink. At least some of the thermal conductive vias are formed extending from the top surface to the bottom surface of the substrate at an angle.

公开(公告)号：US20060240687A1

公开(公告)日：2006-10-26

申请号：US11475479

申请日：2006-06-26

Applicant: Chin Chong ,  Choon Lee

Inventor： Chin Chong ,  Choon Lee

IPC: H01R12/00

CPC classification number: H01R12/526 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09836 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/4922

Abstract: Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting electronic components includes a dielectric portion having a first surface and a second surface. A first terminal is disposed on the first surface of the dielectric portion for connection to a first electronic component. A second terminal is disposed on the second surface of the dielectric portion for connection to a second electronic component. The apparatus further includes a passage extending through the dielectric portion along a longitudinal axis oriented at an oblique angle relative to the first surface. The passage is at least partially filled with conductive material electrically connecting the first terminal to the second terminal.

公开(公告)号：US20060108680A1

公开(公告)日：2006-05-25

申请号：US11285334

申请日：2005-11-22

Applicant: Ching-Yuan Wu ,  Kuang-Jen Liu ,  Chun-Chi Hsu

Inventor： Ching-Yuan Wu ,  Kuang-Jen Liu ,  Chun-Chi Hsu

IPC: H01L23/04 ,  H05K7/06

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09836

Abstract: A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes the steps of providing a first wire layer and forming a first wiring on the first wire layer, forming a middle layer on the first wire layer, forming a second wire layer on the middle layer, forming a slanting via in the middle layer and the second wire layer wherein the direction of the slanting via is not orthogonal to the first and the second wire layers, forming a second wiring on the second wire layer by an etching method, and forming an electroplated layer in the via to connect the first wiring and the second wiring.

Abstract translation: 多层印刷电路板（PCB）包括第一布线层，第一布线层之上的中间层，中间层上方的第二布线层和形成在中间层和第二布线层中的倾斜孔。 该制造方法包括以下步骤：在第一布线层上形成第一布线层并形成第一布线，在第一布线层上形成中间层，在中间层上形成第二布线层，在中间层形成倾斜孔 层和第二线层，其中倾斜通孔的方向不与第一和第二线层正交，通过蚀刻方法在第二线层上形成第二布线，并且在通孔中形成电镀层以连接 第一布线和第二布线。

公开(公告)号：US07024763B2

公开(公告)日：2006-04-11

申请号：US10723269

申请日：2003-11-26

Applicant: Gaetan L. Mathieu ,  Igor Y. Khandros ,  Carl Reynolds

Inventor： Gaetan L. Mathieu ,  Igor Y. Khandros ,  Carl Reynolds

IPC: H05K3/30

CPC classification number: H05K3/42 ,  G01R1/06711 ,  G01R1/07307 ,  G01R3/00 ,  H05K3/308 ,  H05K2201/09836 ,  H05K2203/0338 ,  Y10T29/49117 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49194

Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside. In a third embodiment, a layer of masking material is initially deposited on a substrate and etched to form holes which are filled with a sacrificial fill material, the masking material is then removed, the fill material plated, grinding is performed to remove some plating to expose the fill material, and the fill material is then etched away leaving plated attachment wells. Probes may be attached to the plated through holes or attachment wells to create resilient spring contacts to form a wafer probe card assembly. A twisted tube plated through hole structure is formed by supporting twisted sacrificial wires coated with the plating material in a substrate, and later etching away the wires.

公开(公告)号：US07011988B2

公开(公告)日：2006-03-14

申请号：US11145948

申请日：2005-06-07

Applicant: Robert Forcier

Inventor： Robert Forcier

IPC: H01L21/44

CPC classification number: H05K1/185 ,  B81C1/0023 ,  G02B6/43 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/02333 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/186 ,  H05K2201/09836 ,  H05K2203/061 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/3512

Abstract: A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

Abstract translation: 用于芯片到芯片互连的集成结构和利用多角度通孔的系统级封装，用于电和光路由或电子信息的总线以及包括中间复合材料的受控CTE电介质，以实现单片结构的最佳电气和光学性能。 芯片，多芯片，微机电（MEM）和/或其他有源或无源元件如换能器或电容器可以准确地定位在诸如铜散热片的基板上，并且可以将多角螺柱凸块放置在 组件。 第一电介质层优选地放置在部件上，从而将部件嵌入结构中。 通过光刻，激光加工，软光刻或各向异性导电膜接合的各种工艺，在第一金属层上形成逃逸路线和电路。 使用多角度通孔形成附加介电层和金属电路，以形成从芯片上的紧密间距接合焊盘到其它有源和无源部件的逃逸路由。 多角度通孔可以以数字或模拟电磁电流的形式携带电或光信息，或以可见或不可见的光学总线和互连的形式。

公开(公告)号：US20050087356A1

公开(公告)日：2005-04-28

申请号：US10704131

申请日：2003-11-10

Applicant: Robert Forcier

Inventor： Robert Forcier

IPC: B81B7/00 ,  B81B7/02 ,  G02B6/43 ,  H01L21/60 ,  H01L23/31 ,  H01L23/433 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/02

CPC classification number: H05K1/185 ,  B81C1/0023 ,  G02B6/43 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/02333 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/186 ,  H05K2201/09836 ,  H05K2203/061 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/3512

Abstract: A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

Abstract translation: 用于芯片到芯片互连的集成结构和利用多角度通孔的系统级封装，用于电和光路由或电子信息的总线以及包括中间复合材料的受控CTE电介质，以实现单片结构的最佳电气和光学性能。 芯片，多芯片，微机电（MEM）和/或其他有源或无源元件如换能器或电容器可以准确地定位在诸如铜散热片的基板上，并且可以将多角螺柱凸块放置在 组件。 第一电介质层优选地放置在部件上，从而将部件嵌入结构中。 通过光刻，激光加工，软光刻或各向异性导电膜接合的各种工艺，在第一金属层上形成逃逸路线和电路。 使用多角度通孔形成附加介电层和金属电路，以形成从芯片上的紧密间距接合焊盘到其它有源和无源部件的逃逸路由。 多角度通孔可以以数字或模拟电磁电流的形式携带电或光信息，或以可见或不可见的光学总线和互连的形式。

公开(公告)号：US20040201396A1

公开(公告)日：2004-10-14

申请号：US10832845

申请日：2004-04-27

Inventor： Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs JR.

IPC: G01R031/26

CPC classification number: H01R12/52 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/57 ,  H01R13/2414 ,  H05K3/3436 ,  H05K3/42 ,  H05K7/1061 ,  H05K13/0465 ,  H05K2201/0133 ,  H05K2201/09836 ,  H05K2201/10378 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.