REFERENCE VOLTAGE GENERATION CIRCUIT

    公开(公告)号:JP2000066749A

    公开(公告)日:2000-03-03

    申请号:JP19981399

    申请日:1999-07-14

    Inventor: YON K KIM RYU SEI

    Abstract: PROBLEM TO BE SOLVED: To provide an improved reference voltage generation circuit for generating the output reference voltage of about 700 mV compensated for the fluctuation of a temperature and a power supply voltage by using the extremely low power supply voltage of about 1 V. SOLUTION: The extremely low power supply voltage VCC is used, first and second gate bias voltages are supplied to two P channel transistors P1, P2; P3, P4; P5, P6; P7 and P8 respectively provided in parallelly connected first-forth circuit branches and a current I1 flowing to the first circuit branch is kept constant when the fluctuation is generated in a power supply potential VCC. Thus, a further low reference output voltage Vref compensated for the fluctuation of the temperature and the power supply voltage is generated.

    INTEGRATED CIRCUIT
    12.
    发明专利

    公开(公告)号:JPH11177406A

    公开(公告)日:1999-07-02

    申请号:JP16686398

    申请日:1998-06-15

    Inventor: KUBINEC JAMES J

    Abstract: PROBLEM TO BE SOLVED: To reduce the number of pins by connecting a second filter to a chip function element to constitute a transceiver, exchanging bit data from a power source line to obtain serializing/non-serializing configuration and transferring a signal between chips. SOLUTION: A chip function element 208 of an IC 200 transfers parallel bit data to a transceiver 206 and serializes plural kinds of bit data into a serial data stream. The transceiver 206 outputs it at a high speed, permits it to be a high frequency component with a high-pass filter 204 and transmits it to IC 210 with a power source line Vcc. The high frequency component of the power source line Vcc is extracted by the high-pass filter 214 of IC 210, transmitted to the transceiver 216 to be non-serialized and returned to parallel bit data at the time of transmission. In this way, a serial link is constituted between ICs 200 and 210 with the power source line Vcc. Then, parallel data exchange which is executed conventionally by the plural pins is serially executed through the power source pins and becomes replaceable for a single power source pin.

    ZERO CURRENT DRAW CIRCUIT
    13.
    发明专利

    公开(公告)号:JPH1117119A

    公开(公告)日:1999-01-22

    申请号:JP35274997

    申请日:1997-12-22

    Inventor: AN JIU

    Abstract: PROBLEM TO BE SOLVED: To reduce a leakage current in an integrated circuit device, by a method wherein a zero current draw circuit is connected between bonding pads on an integrated circuit and the internal circuit of the integrated circuit. SOLUTION: An integrated circuit 10 has a cavity 22 for housing an internal circuit 100. Package leads 24 for connecting the circuit 100 with an external device are formed along the peripheral edge parts of a chip package 20. Bonding pads 30 are used for connecting the circuit 100 with the leads 24. A zero-current draw circuit 50 is coupled between the pads 30 and the circuit 100 and in the normal operating mode of the circuit 50, the circuit 50 is coupled between the pads 30 and a ground potential. As the pads 30 are pulled to the ground potential through a pull-down transistor which is turned on in a default constitution, a leakage current is not pulled in an integrated circuit device at all.

    CONTROLLER FOR WIRELESS LOCAL AREA NETWORK(WLAN), METHOD FOR DYNAMICALLY ADJUSTING OPERATION PARAMETER OF WLAN AND CONTROLLER FOR RADIO COMMUNICATION STATION

    公开(公告)号:JPH10303930A

    公开(公告)日:1998-11-13

    申请号:JP2837998

    申请日:1998-02-10

    Abstract: PROBLEM TO BE SOLVED: To obtain the most possible WLAN(wireless local network) throughput to a current operation conduction by dynamically adjusting PTS/CTS threshold and division threshold. SOLUTION: A monitor/adjusting unit 112 receives a TX state and medium reservation state information from a data processing unit 102 and decides a value that dynamically adjusts RTS/CTS threshold and division threshold. It specifically monitors data transmission to each of (n+1) destination addresses in a WLAN and calculates DA (0...n) RTS threshold and DA(0...n) Frag threshold which represent the RTS/CTS threshold and the division threshold which are separately and dynamically adjusted to each destination address in the WLAN. Also, STA RTS threshold that represents an average RTS/CTS threshold level which is adjusted to an entire WLAN is given to a TX queuing unit 104 and a TX unit 108.

    CIRCUIT TO ELIMINATE GLITCH SIGNAL
    15.
    发明专利

    公开(公告)号:JPH10290146A

    公开(公告)日:1998-10-27

    申请号:JP67598

    申请日:1998-01-06

    Abstract: PROBLEM TO BE SOLVED: To provide the glitch eater circuit that eliminates a glitch signal caused within a predetermined period from a leading edge or a trailing edge of a signal pulse. SOLUTION: A glitch eater circuit includes an inverter connecting to a transmission gate 52 controlled by a 2-input XNOR (exclusive NOR) gate 58 that receives a latched signal at one input and receives a delayed and latched signal at the other input and the latched signal comes from the transmission gate 52. The latched signal is reset by a transistor(TR) 80.

    COMPUTER PROCESS FOR IDENTIFYING AND CORRECTING ERROR INSIDE CENTRAL PROCESSING UNIT

    公开(公告)号:JPH10105443A

    公开(公告)日:1998-04-24

    申请号:JP12842597

    申请日:1997-05-19

    Abstract: PROBLEM TO BE SOLVED: To provide a method for identifying an error inside a central processing unit(CPU) during the execution of a software and correcting the identified error. SOLUTION: CPU repeatedly interrupts the execution of the software so as save a CPU state (130A). When the error occurs during execution, CPU saves the state again and, after that, gives control to a handler for processing the error. The error can be debugged by off-line by successively loading the saved CPU state into a development system and reproducing an error condition in the system. The error can be also debugged by executing foreseeing through the use of an instruction which is recognized as the error and a corresponding correcting instruction even before the occurrence of the error. Thus, the recognized error is easily prevented. Moreover, even unless the error is debugged, the temporary correcting instruction is used so as to enable ending an application (120A).

    METHOD FOR PROCESSING OF INTERRUPT ROUTINE BY DIGITAL INSTRUCTION PROCESSOR CONTROLLER

    公开(公告)号:JPH09171463A

    公开(公告)日:1997-06-30

    申请号:JP28379296

    申请日:1996-10-25

    Abstract: PROBLEM TO BE SOLVED: To enable a completely exact branching prediction without dividing the pipeline of an instruction and without requesting a complicated circuit, by fetching a saved instruction for the pipeline. SOLUTION: A multiplexor(MUX) 26 receives the control signal based on a branching condition, imparts either one of the branching target address imparted on a data route 24 and the continuous address imparted on a data route 20 to an instruction cache 30 and determines whether the next instruction to be executed by a processor 10 is fetched or not. When the instruction requesting a branching is processed by the processor 10 so as not to generate the branching till the instruction succeeding the branching instruction is executed. The instruction pipeline realized by a PC stack pipeline 32 in this way operates without an interruption even when the branching instruction enters the pipeline. Therefore, the branching is made to be generated within the single cycle of the assigned pipeline.

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