公开(公告)号：EP4421872A1

公开(公告)日：2024-08-28

申请号：EP23204516.1

申请日：2023-10-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pandey, Shesh Mani ,  Shanbhag, Kaustubh ,  Krishnasamy, Rajendran ,  Holt, Judson R.

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/336 ,  H01L29/16

CPC classification number: H01L29/7835 ,  H01L29/66659 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/665 ,  H01L29/16

Abstract: Disclosed are embodiments of a structure including a semiconductor layer and a device, which has a well region within the semiconductor layer and at least one porous region within and shallower in depth than the well region. In some embodiments, the device can be a field effect transistor (FET) (e.g., a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFETs)) with a drain drift region that extends through the well region around the porous region(s) to a drain region. The porous region(s) can modify the electric field in this drain drift region, thereby improving device performance. Embodiments can vary with regard to the number, size, shape, configuration, etc. of the porous region(s) within the well region. Also disclosed herein are method embodiments for forming the semiconductor structure.

公开(公告)号：EP4418268A1

公开(公告)日：2024-08-21

申请号：EP23191931.7

申请日：2023-08-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chinthu, Siva Kumar ,  Pasupula, Suresh ,  Dwivedi, Devesh

IPC: G11C7/06

CPC classification number: G11C7/065

Abstract: Disclosed are a sense circuit and memory structure incorporating the sense circuit. The sense circuit is connected to voltage rails at VDD1 and VDD2, respectively, where VDD2~1/2∗VDD1. During a sensing operation, VDD1 provides power to develop a voltage differential between Vdata and Vref on sense nodes. A voltage comparator samples Vdata and Vref and, based on a detectable voltage differential (minVdiff), outputs a data output value. To increase the speed at which minVdiff is reached, an equalization process is performed at the initiation of the sensing operation and includes using pre-charge transistors to quickly equalize the sense nodes to VDD2. Following equalization, Vdata and Vref only need to be pulled up or down from VDD2. Thus, minVdiff is reached faster and sampling by the voltage comparator can be performed earlier in time, reducing the overall time required for performing the sensing operation and for powering the sense circuit.

公开(公告)号：EP4383344A3

公开(公告)日：2024-08-21

申请号：EP23206288.5

申请日：2023-10-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： SHARMA, Santosh ,  ZIERAK, Michael J. ,  LEVY, Mark D. ,  BENTLEY, Steven J.

IPC: H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7786 ,  H01L29/7783 ,  H01L29/7781 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/402

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bidirectional device, methods of manufacture and methods of operation. The structure includes: a first gate structure (19a) adjacent to a first source region (23a); a second gate structure (19b) adjacent to a second source region (23b); and field plates (22) adjacent to the first gate structure, the second gate structure and a surface of an active layer (20) of the first gate structure and the second gate structure.

公开(公告)号：EP4415266A1

公开(公告)日：2024-08-14

申请号：EP23195920.6

申请日：2023-09-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Soh, Mei Yu

IPC: H03K19/017 ,  H03K19/0944

CPC classification number: H03K19/01714 ,  H03K19/09443

Abstract: A GaN logic circuit (210) may include an input node (IN) receiving an input voltage, a first pull up transistor (218) pulling up an output voltage (OUT) in response to the input voltage (IN), and a first depletion mode transistor (220) having a first gate (G1) to which a first gate voltage (VG1) is applied and a second gate (G2) to which a second gate voltage (VG2) is applied. The first depletion mode transistor (220) may control the first pull up transistor (218) in response to a gate voltage difference (VG1 - VG2) between the first gate voltage (VG1) and the second gate voltage (VG2). The logic device may further include a capacitor (216) having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.

公开(公告)号：EP4401120A1

公开(公告)日：2024-07-17

申请号：EP23195335.7

申请日：2023-09-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Xu, Dewei ,  Wu, Zhuojie ,  Smith, Daniel

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/7682 ,  H01L23/481 ,  H01L21/76898

Abstract: A structure includes a through semiconductor via (TSV) in a semiconductor substrate, and a dielectric liner surrounding the TSV and between the TSV and the semiconductor substrate. A plurality of discontinuous air gaps is in the semiconductor substrate extending away from the dielectric liner, e.g., radially. The discontinuous air gaps reduce the parasitic coupling capacitance and relieve stress in the semiconductor substrate.

公开(公告)号：EP4400935A1

公开(公告)日：2024-07-17

申请号：EP23214852.8

申请日：2023-12-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： ECKHARDT, Uwe

IPC: G05F3/24 ,  G05F3/30

CPC classification number: G05F3/30 ,  G05F3/242

Abstract: The present disclosure relates to a structure including a first curvature compensation circuit which includes a first set of transistors, and a second curvature compensation circuit which includes a second set of transistors. A voltage reference (VREF) signal output from a bandgap voltage reference core with the second curvature compensation circuit is received as an input to the first curvature compensation circuit.

公开(公告)号：EP4386852A1

公开(公告)日：2024-06-19

申请号：EP23202301.0

申请日：2023-10-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pandey, Shesh Mani

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7824 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/66681

Abstract: A semiconductor device comprises a semiconductor layer over an insulator layer and a base layer under the insulator layer. A drain region comprises a well in the base layer, a doped region above and coupled with the well, a first drift region above and coupled with the first region, and a second drift region above the first doped region. The first doped region is at least partially in the insulator layer and the first drift region is at least partially in the semiconductor layer. A trench isolation structure is within the drain region and a gate stack is partially over the semiconductor layer and overlapping the first drift region.

公开(公告)号：EP4383344A2

公开(公告)日：2024-06-12

申请号：EP23206288.5

申请日：2023-10-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： SHARMA, Santosh ,  ZIERAK, Michael J. ,  LEVY, Mark D. ,  BENTLEY, Steven J.

IPC: H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L29/7783 ,  H01L29/7781 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bidirectional device, methods of manufacture and methods of operation. The structure includes: a first gate structure (19a) adjacent to a first source region (23a); a second gate structure (19b) adjacent to a second source region (23b); and field plates (22) adjacent to the first gate structure, the second gate structure and a surface of an active layer (20) of the first gate structure and the second gate structure.

公开(公告)号：EP4372823A1

公开(公告)日：2024-05-22

申请号：EP23202868.8

申请日：2023-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： JAIN, Vibhor ,  JOHNSON, Jeffrey ,  ONTALUS, Viorel ,  PEKARIK, John J.

IPC: H01L29/06 ,  H01L21/331 ,  H01L29/737 ,  H01L29/08

CPC classification number: H01L29/7371 ,  H01L29/66242 ,  H01L29/0649 ,  H01L29/0821

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an emitter, a collector including a first section, a second section, and a third section positioned in a first direction between the first section and the second section, and an intrinsic base disposed in a second direction between the emitter and the third section of the collector. The structure further comprises a stress layer including a section positioned to overlap with the emitter, the intrinsic base, and the collector. The section of the stress layer is surrounded by a perimeter, and the first and second sections of the collector are each positioned adjacent to the perimeter of the stress layer.

公开(公告)号：EP4372818A1

公开(公告)日：2024-05-22

申请号：EP23192845.8

申请日：2023-08-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Karalkar, Sagar Premnath ,  Zeng, Jie ,  Mitra, Souvick

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/735

CPC classification number: H01L27/0259 ,  H01L29/735 ,  H01L29/0634 ,  H01L29/0623

Abstract: The disclosure provides a structure with a buried doped region, and methods to form the same. A structure may include a semiconductor substrate including a first well. A first terminal includes a first doped region in the first well. A second terminal includes a second doped region in the first well. The first well horizontally separates the first doped region from the second doped region. A first buried doped region is in the first well. The first buried doped region overlaps with, and is underneath, the first doped region. The first well vertically separates the first doped region from the first buried doped region.