公开(公告)号：JPH10321833A

公开(公告)日：1998-12-04

申请号：JP8317698

申请日：1998-03-30

Applicant: ST MICROELECTRON INC

Inventor： NGUYEN LOI N

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/108 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To reduce the aspect ratio of a contact and, at the same time, to increase the area of the contact by forming a gate composed of polysilicon or a poly-silicide having at least one surface nonperpendicularly to a substrate on at least one side wall. SOLUTION: A gate 48 (poly 1 layer) which has a chamfered surface 50 which is formed nonperpendicularly to the main surface of a substrate 42 and is made of polysilicon or a poly-silicide is formed on a gate oxide layer 44. Although a local interconnecting body 58 (poly 2 layer) is formed thereafter, the body 58 is separated from the chamfered surface 50 of the gate 48 by the minimum distance 'y' between a side-wall adaptive corner section 60 formed between the side wall of the gate 48 and the chamfered surface 50 and the nearest point 62 on the body 58. Thus an improved separating distance can be obtained between the poly 1 and 2 layers and, at the same time, a self-aligned contact can be realized.

公开(公告)号：JPH10240615A

公开(公告)日：1998-09-11

申请号：JP35423697

申请日：1997-12-24

Applicant: ST MICROELECTRON INC

Inventor： LYSINGER MARK A

IPC: G06F12/06 ,  G11C7/10 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To improve operation speed by transferring decoded memory address information from a second decoded address storage circuit to a first decoded address storage circuit. SOLUTION: A memory device 50 has a memory array 52 and the memory array 52 is subdivided into plural memory array blocks 54. The memory circuit has plural data storage positions and addresses related to the respective data storage positions. The first decoded address storage circuit stores the first decoded memory address and holds it for access to the specified memory address. The second decoded address storage circuit stores the second decoded memory address and holds it for access to the second decoded memory address. A control circuit operates in such a way that decoded memory address information is transferred to the first decoded address storage circuit from the second decoded address storage circuit.

公开(公告)号：JP2014060395A

公开(公告)日：2014-04-03

申请号：JP2013183545

申请日：2013-09-05

Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc.

Inventor： ZHANG JOHN H

IPC: H01L21/66 ,  G01R29/24 ,  H01L21/02

CPC classification number: H01L22/12 ,  B24B37/005 ,  B24B37/04 ,  B24B49/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an improved apparatus and method for performing measurement of a wafer.SOLUTION: The apparatus may include a substrate with a plurality of microprobes. A plurality of light sources may direct light onto each of the microprobes. Light reflected from the microprobes may be detected by a plurality of photodetectors, thereby detection signals each of which is associated with one of the microprobes are generated. A controller may send a driving signal to each of the plurality of microprobes, and may determine a height distribution and a surface charge distribution of the wafer on the basis of the detection signals.

Abstract translation: 要解决的问题：提供一种用于进行晶片测量的改进的装置和方法。解决方案：该装置可以包括具有多个微探针的基板。 多个光源可以将光引导到每个微探针上。 可以由多个光电检测器检测从微探针反射的光，从而产生与微探针之一相关联的检测信号。 控制器可以向多个微探针中的每一个发送驱动信号，并且可以基于检测信号来确定晶片的高度分布和表面电荷分布。

公开(公告)号：JP2014042020A

公开(公告)日：2014-03-06

申请号：JP2013164180

申请日：2013-08-07

Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc.

Inventor： LIU QING ,  NICOLAS LOUBET ,  PRASANNA KHARE

IPC: H01L21/762 ,  H01L21/336 ,  H01L21/76 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/76283 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76264

Abstract: PROBLEM TO BE SOLVED: To provide an electronic apparatus capable of improving interface properties between a shallow trench isolation (STI) region and a corresponding semiconductor device, and a method for manufacturing the same.SOLUTION: An electronic apparatus can comprise a substrate, a buried type oxide (BOX) layer on the substrate, at least one of semiconductor device on the BOX layer, and at least one of STI region adjacent to at least one of semiconductor device and in the substrate. At least one of STI region can comprise a nitride layer defining a sidewall surface of the substrate and lining a bottom part of the sidewall surface, an oxide layer lining an upper part of the sidewall surface above the bottom part, and an insulating material in the nitride layer and the oxide layer.

Abstract translation: 要解决的问题：提供一种能够改善浅沟槽隔离（STI）区域和对应的半导体器件之间的界面特性的电子设备及其制造方法。解决方案：电子设备可以包括衬底，埋置 氧化物（BOX）层，BOX层上的半导体器件中的至少一个以及与半导体器件和衬底中的至少一个相邻的STI区域中的至少一个。 STI区域中的至少一个可以包括限定衬底的侧壁表面并且衬里侧壁表面的底部的氮化物层，衬在底部部分上方的侧壁表面的上部的氧化物层，以及位于衬底的绝缘材料 氮化物层和氧化物层。

公开(公告)号：JPH11111872A

公开(公告)日：1999-04-23

申请号：JP21785498

申请日：1998-07-31

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU ,  SAGARWALA PERVEZ H ,  NGUYEN LOI

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To improve the insulation by providing an oxide layer having an increased thickness between the outer end of a polysilicon silicide layer and substrate disposed blow it. SOLUTION: A thin porous oxide is deposited at a comparatively low temp. to surround a polysilicon silicide layer 228, and this layer is anisotropically etched to form a pattern i.e., the lower corners 278 of a polysilicon layer 234 are rounded, compared with in prior art, to locate slightly apart from the top surface of an underlying n-type region 210 and the rounded corners are slightly laterally displaced from the boundary 276 of a side wall oxide spacer 230. These structures at the ends of a tunnel oxide layer 226 greatly improve the dielectric completeness at the lower corners of the polysilicon layer 228 by an oxidizing process for converting some of Si in the polysilicon layer 234 and a small amt. of the top surface of a substrate 206 into Si dioxide.

公开(公告)号：JPH11103020A

公开(公告)日：1999-04-13

申请号：JP20159598

申请日：1998-07-16

Applicant: ST MICROELECTRON INC

Inventor： GROOVER ROBERT

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/08 ,  H03M1/74

Abstract: PROBLEM TO BE SOLVED: To improve the scaling accuracy by pairing a square capacitor with a rectangular capacitor having the same perimeter to cancel the contribution of end elements with that of corner elements. SOLUTION: A differential pair of capacitors C6 A, C6 B are divided in capacitive elements. The capacitor C6 A is composed of four corner capacitor elements CC, 28 end capacitive elements CE at the ends and inner capacitive elements C1 to which capacitance contributions proportional, directly to their areas are added. Additive contributions determined by the capacitance coupling in the area 199 adjacent the ends are added so as to cancel peripheral capacitance contributions of the capacitances C6 A and C6 B, when using the capacitor differential coupling.

公开(公告)号：JPH1195847A

公开(公告)日：1999-04-09

申请号：JP19335898

申请日：1998-07-08

Applicant: ST MICROELECTRON INC

Inventor： MAIKERU JIEI KARAHAN JIYUNIA ,  UIRIAMU II EDOWAAZU

IPC: G05F1/56 ,  G05F1/565 ,  G05F1/575 ,  H02J1/00

Abstract: PROBLEM TO BE SOLVED: To increase the stability without increasing power dissipation by making a switched capacitor operate to vary the zero of the voltage regulator as a function of its output current. SOLUTION: An error amplifier 24 compares a reference voltage VREF with a regulated voltage VREG supplied to the error amplifier 24 through a feedback circuit consisting of a resistance 34 and a resistance 36. Resistances 34 and 36 are constituted as a voltage divider for scaling the regulator voltage VREG and feeds the scaled voltage to the inverted input terminal of the error amplifier 24. The integrator consisting of the amplifier 26, the switched capacitor 30, and a capacitor 32 has zero having a frequency represented as fZERO=1/2πC32 Reff (Reff =1/fVCOC30 ), so a pass transistor 28 regulates a voltage source VDD in response to the output of the error amplifier 24 and integrator, and then generates the regulated voltage VREF.

公开(公告)号：JPH1169872A

公开(公告)日：1999-03-09

申请号：JP15081998

申请日：1998-06-01

Applicant: ST MICROELECTRON INC

Inventor： CAROBOLANTE FRANCESCO

IPC: G11B21/10 ,  G11B21/08 ,  H02P25/02 ,  H02P25/06 ,  H02P7/00

Abstract: PROBLEM TO BE SOLVED: To change a through rate, by conducting selective connection to a voltage supply source in response to a driver signal connected to inductive load and received by an input terminal, and performing through rate control of voltage on inductive load in response to a through rate control signal received from a through rate control circuit. SOLUTION: A signal which a reading head 24 supplies include positional data on a rotating disc 26. A microprocessor 14 controls a driver circuit 12 with a through rate control signal and an analog control signal 20. The through rate control circuit 11 supplies the through rate control signal to the driver circuit 12 as a power supply signal. When the microprocessor 14 supplies a digital control signal 16 to a digital-analog converter 18, a DAC18 converts it into an analog control signal 20 to apply it to the input terminal of the driver circuit 12. The driver circuit 12 drives PWM current in the forward and reverse directions through a coil, and conducts acceleration/deceleration in response to the current to position the reading head 24 above a rotating disc 26.

公开(公告)号：JPH1166510A

公开(公告)日：1999-03-09

申请号：JP16246798

申请日：1998-06-10

Applicant: ST MICROELECTRON INC

Inventor： MARK H RIATTO

IPC: G11B5/09 ,  G01R33/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B33/12

Abstract: PROBLEM TO BE SOLVED: To improve a bias method of pre-amplifier and MR sensor by supplying a current bias to an MR sensor from a pre-amplifier and then amplifying, with a pre-amplifier, change of electric resistance output, responding to such current bias, from the MR sensor by detecting change of magnetic data flux. SOLUTION: In an integrated circuit 15 for pre-amplifying of a preamplifier 10, a current source sensor bias circuit 20 supplies a current bias to an MR sensor R via a current bias loop circuit 25 from the supply voltage. The loop circuit 25 detects and outputs a change of current bias depending on change of electric resistance due to magnetic data flux by the MR sensor. This output is amplified and output by a first and a second amplifying circuits A1, A2 and an amplifying output circuit 35 and an output current of a stabilizing circuit 38 drives the first amplifying circuit A1 to bias the MR sensor R. Thereby, the bias method of the pre-amplifier for hard disk drive and MR sensor can be improved.

公开(公告)号：JPH1145948A

公开(公告)日：1999-02-16

申请号：JP14925298

申请日：1998-05-29

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU

IPC: H01L21/8244 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To enhance the operational characteristics of a cell while minimizing the geometry by constituting an SRAM memory cell of two storage transistors and two access transistors with four gates of these transistors being arranged all in the same direction. SOLUTION: Each set comprising four memory cells is arranged symmetrically to the source region 38 for each memory cell in a group. All gate electrodes formed of a first polysilicon layer are substantially parallel with each other and extend substantially linearly. Deviation from a line is less than one half of its own width and thereby lines 57, 59 can be located at an arbitrary position over one half of the width of gate electrode. Since linear and parallel storage transistors 12, 14 and word lines 32 are provided, operation of the cell is stabilized resulting in the enhancement of reliability and electric operation of a memory cell.