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    SENSING DEVICE PACKAGE STRUCTURE
    14.
    发明公开
    SENSING DEVICE PACKAGE STRUCTURE 审中-公开

    公开(公告)号：EP3780075A1

    公开(公告)日：2021-02-17

    申请号：EP20197731.1

    申请日：2012-08-16

    Applicant: Unimicron Technology Corp.

    Inventor： CHEN, Tsung-Yuan ,  CHENG, Wei-Ming

    IPC: H01L21/56 ,  H01L27/146 ,  H01L31/0203 ,  H01L21/60 ,  H01L23/485 ,  H01L23/31

    Abstract: A sensing device package structure including a middle dielectric layer, a sensing device, a front dielectric layer, a front patterned conductive layer and at least one front conductive via is provided. The middle dielectric layer has an anterior surface, a posterior surface and a middle opening. The sensing device is disposed in the middle opening. The sensing device has a front surface, a back surface, a sensing region, a blocking pattern, and at least one electrode. The front dielectric layer is disposed on the anterior surface of the middle dielectric layer and the front surface of the sensing device. The front dielectric layer has a front opening exposed the sensing region and the blocking pattern. The front patterned conductive layer is disposed on the front dielectric layer. The front conductive via penetrates through the front dielectric layer and connects the front patterned conductive layer and the electrode.

    Semiconductor packaging structure and method of fabricating the same
    18.
    发明公开
    Semiconductor packaging structure and method of fabricating the same 审中-公开
    半导体封装结构及其制备方法

    公开(公告)号：EP2560201A3

    公开(公告)日：2014-07-02

    申请号：EP11194105.0

    申请日：2011-12-16

    Applicant: Unimicron Technology Corp.

    Inventor： Hu, Dyi-Chung ,  Hu, Yu-Shan

    IPC: H01L23/36 ,  H01L23/367 ,  H01L23/538

    CPC classification number: H01L23/5389 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00015 ,  H01L2924/00

    Abstract: A semiconductor packaging structure includes a semiconductor chip, a packaging layer, a dielectric layer, a wiring layer, and a metallic foil. The semiconductor chip has an active surface, an inactive surface opposing the active surface, electrode pads formed on the active surface, and metal bumps formed on the electrode pads. The packaging layer encapsulates the semiconductor chip and exposes the active surface. The dielectric layer is formed on the active surface and a surface of the packaging layer at the same side with the active surface, and has wiring pattern openings for the metal bumps to be exposed therefrom. The wiring layer is formed in the wiring pattern openings. The metallic foil is disposed on the packaging layer adjacent to the inactive surface. Metallic protrusions are formed on the metallic foil, and penetrate the packaging layer to extend to the inactive surface of the semiconductor chip.

    ELECTROCHROMIC MIRROR MODULE
    19.
    发明公开
    ELECTROCHROMIC MIRROR MODULE 审中-公开

    公开(公告)号：EP3828627A2

    公开(公告)日：2021-06-02

    申请号：EP20197966.3

    申请日：2020-09-24

    Applicant: Unimicron Technology Corp.

    Inventor： Lee, An-Sheng ,  Chan, Meng-Chia ,  Hsu, Ming-Yuan ,  Chang, Po-Ching ,  Lin, Shih-Yao ,  Weng, Cheng-Ming

    IPC: G02F1/157 ,  B60R1/08

    Abstract: An electrochromic mirror module including a light-transmissive substrate, an opaque touch sensing layer and an electrochromic device is provided. The light-transmissive substrate has a visible surface and a back surface disposed opposite to the visible surface. The opaque touch sensing layer and the electrochromic layer are disposed on the back surface. Distribution areas of the opaque touch sensing layer and the electrochromic layer are different on the back surface. An electrochromic mirror module including reflective layer and electrochromic device is also provided.

    Packaging substrate having interposer
    20.
    发明公开
    Packaging substrate having interposer 审中-公开
    包装基材具有内插器

    公开(公告)号：EP2669935A3

    公开(公告)日：2017-12-27

    申请号：EP12191602.7

    申请日：2012-11-07

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang, Tseng ,  Dyi-Chung, Hu

    IPC: H01L21/48 ,  H01L23/498

    Abstract: A packaging substrate (100) including following elements is provided. The insulation supporting layer (120) is disposed on a first surface (112) of the multilayered interconnect board (110) and has an opening region (R10). A portion of the first surface (112) is exposed at the opening region (R10). The interposer (130) is disposed on the first surface (112) at the opening region (R10). A third surface (130A) of the interposer (130) faces the first surface (112) of the multilayered interconnect board (110). A stress releasing gap (136) is between an outer-sidewall of the interposer (130) and an inner-sidewall of the opening region (R10). The compliant layer (170) is disposed between the third surface (130A) and the first surface (112). The interposer (130) has through holes (132) and conductive posts (134) disposed in the through holes (132). The conductive posts (134) penetrate the compliant layer (170) and electrically connect with the multilayered interconnect board (110). The redistribution layer (140) is disposed on a fourth surface (130B) of the interposer (130) and is electrically connected with the conductive posts (134).

    Abstract translation: 提供了包括以下元件的封装基板（100）。 绝缘支撑层（120）设置在多层互连板（110）的第一表面（112）上并具有开口区域（R10）。 第一表面（112）的一部分在开口区域（R10）处暴露。 中介层（130）在开口区域（R10）处设置在第一表面（112）上。 中介层（130）的第三表面（130A）面向多层互连板（110）的第一表面（112）。 应力释放间隙（136）位于插入件（130）的外侧壁与开口区域（R10）的内侧壁之间。 柔性层（170）设置在第三表面（130A）和第一表面（112）之间。 中介层（130）具有设置在通孔（132）中的通孔（132）和导电柱（134）。 导电柱（134）穿过柔性层（170）并与多层互连板（110）电连接。 再分布层140设置于中介层130的第四表面130B上并与导电柱134电性连接。

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