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公开(公告)号：KR1020100090883A
公开(公告)日：2010-08-18
申请号：KR1020090010093
申请日：2009-02-09
Applicant: 삼성전기주식회사
CPC classification number: H01L24/96 , H01L21/568 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/92 , H01L2924/01033 , H01L2924/01059 , H01L2924/01075 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2224/96 , H01L2224/82 , H01L2924/00 , H01L2924/00012
Abstract: PURPOSE: A method for manufacturing a wafer level package is provided to prevent the warpage of a package during the curing process of a molding material by forming the molding material in a space between pluralities of chips. CONSTITUTION: A plurality of chips(110) is mounted on one side of a supporting unit. A molding material(120) is formed in a space between the pluralities of chips. The molding material is formed by a printing method using a printing mask. The printing mask opens the space between the pluralities of chips. The supporting unit is eliminated. An insulating layer including a re-distribution wiring(140) is formed on one side of the molding material including the chip. The re-distribution wiring is connected with the pads of the chips. An external connecting unit is formed to be connected with the re-distribution wiring.
Abstract translation: 目的：提供一种制造晶片级封装的方法，以通过在多个芯片之间的空间中形成模制材料来防止在模制材料的固化过程中封装的翘曲。 构成：多个芯片（110）安装在支撑单元的一侧。 模制材料（120）形成在多个芯片之间的空间中。 成型材料通过使用印刷掩模的印刷方法形成。 打印掩模打开多个芯片之间的空间。 支持单元被消除。 在包括芯片的成型材料的一侧上形成包括再分配布线（140）的绝缘层。 再分配线路与芯片的焊盘连接。 外部连接单元形成为与再分配配线连接。
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公开(公告)号：KR1020100083382A
公开(公告)日：2010-07-22
申请号：KR1020090002727
申请日：2009-01-13
Applicant: 삼성전기주식회사
IPC: H05K3/24
Abstract: PURPOSE: The method of repairing of the patterned portion is that the self-assembled monolayer is formed in the repair circuit domain. The interface neighborhood adhesion is improved. CONSTITUTION: The fault whether or not of the patterned portion(104) is tested. The conductive material(110) is filled in the open bad sector of above pattern unit. The conductive material is filled with the dispenser(108). The conductive material is sintered. The self-assembled monolayer is formed in the sintered conductive material as described above.
Abstract translation: 目的：修复图案部分的方法是在修复电路领域形成自组装单层。 界面附着力提高。 构成：是否测试图案化部分（104）的故障。 导电材料（110）填充在上述图案单元的开口坏扇区中。 导电材料被分配器（108）填充。 导电材料被烧结。 如上所述，在烧结的导电材料中形成自组装单层。
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公开(公告)号：KR1020100071485A
公开(公告)日：2010-06-29
申请号：KR1020080130219
申请日：2008-12-19
Applicant: 삼성전기주식회사
IPC: H01L21/78 , H01L21/301
CPC classification number: H01L21/561 , H01L23/24 , H01L23/3121 , H01L24/94 , H01L2924/09701 , H01L2924/181 , H01L2924/3511 , H01L2924/00
Abstract: PURPOSE: A method for manufacturing a wafer level package is provided to reduce stress due to thermal expansion coefficient differences between an encapsulating material and a substrate wafer. CONSTITUTION: A plurality of pads(113), a chip(115), a dicing line are formed on a substrate wafer(110). An external connection unit(120) is formed on the pad. A resin is coated on the dicing line. An encapsulating material(150) is coated on the chip positioned between resins. The resin coated on the dicing line is removed.
Abstract translation: 目的：提供一种用于制造晶片级封装的方法，以减少由于封装材料和衬底晶片之间的热膨胀系数差引起的应力。 构成：在基板晶片（110）上形成多个焊盘（113），芯片（115），切割线。 外部连接单元（120）形成在垫上。 在切割线上涂覆树脂。 将封装材料（150）涂覆在位于树脂之间的芯片上。 去除涂覆在切割线上的树脂。
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公开(公告)号：KR1020150062545A
公开(公告)日：2015-06-08
申请号：KR1020130147315
申请日：2013-11-29
Applicant: 삼성전기주식회사
CPC classification number: G03F7/168 , G03F7/36 , G03F7/40 , G03F7/70708 , G03F7/70758 , H01L21/67109
Abstract: 본발명은소프트베이크장치에관한것이다. 본발명에따른소프트베이크장치는포토레지스트가형성된기판을고정하며, 기판을가열하는핫 플레이트; 및상기핫 플레이트상면을밀폐시켜수직이동에따라내부공기를가압하는챔버커버; 를포함하여핫 플레이트상면에고정되는기판을공기로가압하여소프트베이킹의효율을증대시킬수 있는효과가있다.
Abstract translation: 本发明涉及一种软烘烤装置。 根据本发明的软烘烤装置包括：用于固定其上形成有光致抗蚀剂的基板的加热板，并加热基板; 以及用于密封热板的上表面并通过垂直运动按压内部空气的室盖。 固定在加热板的上表面的基板被空气按压，从而提高软烘烤效率。
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公开(公告)号：KR1020120072830A
公开(公告)日：2012-07-04
申请号：KR1020100134736
申请日：2010-12-24
Applicant: 삼성전기주식회사
IPC: H01L23/12
CPC classification number: H01L23/498 , H01L2924/00013 , H01L2924/0002 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
Abstract: PURPOSE: A substrate for a package and a manufacturing method thereof are provided to improve adhesion between the surface of an insulation layer and a seed layer by forming illuminance with a preset size and a preset pattern on the insulation layer. CONSTITUTION: A connection pad(115) electrically connected to an inner circuit is formed on the upper side of a base substrate(110). An insulation layer(150) protects the surface of the base substrate. A via hole is formed in the insulation layer to expose the connection pad of the base substrate. An illuminance(180) with a preset size and a preset pattern is formed on the insulation layer. A seed layer includes a first seed layer(160) and a second seed layer(170) which are successively formed.
Abstract translation: 目的：提供一种用于封装的基板及其制造方法，以通过在绝缘层上形成预定尺寸和预置图案的照度来改善绝缘层的表面与种子层之间的粘合性。 构成：电连接到内部电路的连接焊盘（115）形成在基底（110）的上侧。 绝缘层（150）保护基底基板的表面。 在绝缘层中形成通孔以露出基底衬底的连接焊盘。 在绝缘层上形成具有预设尺寸和预设图案的照度（180）。 种子层包括连续形成的第一种子层（160）和第二种子层（170）。
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Patent Agency Ranking
公开(公告)号：KR101055593B1
公开(公告)日：2011-08-08
申请号：KR1020090002727
申请日：2009-01-13
Applicant: 삼성전기주식회사
IPC: H05K3/24
Abstract: 본 발명은 패턴부의 리페어 방법에 관한 것으로, (A) 패턴부의 오픈 불량부에 도전성 재료를 충진하는 단계, (B) 상기 도전성 재료를 소결하는 단계, 및 (C) 접착력 향상을 위해 상기 소결된 도전성 재료에 자기 조립 단분자막(self-assemble monolayer; SAM)을 형성하는 단계를 포함하는 것을 특징으로 하며, 미세패턴에도 대응이 가능하며, 리페어 수율이 증대될 수 있을 뿐만 아니라, 리페어 회로의 계면 접착력을 향상시킬 수 있는 패턴부의 리페어 방법을 제공한다.
패턴부, 리페어, 오픈 불량부, 페이스트, 소결, 자기 조립 단분자막, 메탈 잉크-
公开(公告)号：KR1020090120855A
公开(公告)日：2009-11-25
申请号：KR1020080046878
申请日：2008-05-21
Applicant: 삼성전기주식회사
CPC classification number: H01L2224/10 , H01L2224/13 , H01L2224/13022 , H01L2224/94 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012
Abstract: PURPOSE: A wafer level package and manufacturing method for forming a groove on a surface of a molding resin are provided to increase manufacturing process yield and improve heat emission efficiency by forming the grove on the surface of molding resin. CONSTITUTION: A wafer level package includes a wafer(10), a distributed wiring(40), an under metal bump, and a molding resin. The wafer includes a chip pad(20). The distributed wiring is formed and electrically connected to the chip pad on the chip pad. The under metal bump is electrically connected to the distributed wiring. The under metal bump is formed on the under metal bump. The molding resin is molded on the top of the wafer.
Abstract translation: 目的：提供一种用于在模制树脂的表面上形成凹槽的晶片级封装和制造方法，以通过在模制树脂的表面上形成凹槽来提高制造工艺的产量并提高散热效率。 构成：晶片级封装包括晶片（10），分布布线（40），金属下凸块和模制树脂。 晶片包括芯片焊盘（20）。 分布式布线形成并电连接到芯片垫上的芯片焊盘。 底部金属凸块电连接到分布式布线。 底部金属凸块形成在下面的金属凸块上。 模塑树脂被模制在晶片的顶部上。
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公开(公告)号：KR1020120007444A
公开(公告)日：2012-01-20
申请号：KR1020110062517
申请日：2011-06-27
Applicant: 삼성전기주식회사
CPC classification number: H05K3/4602 , H01L23/145 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K1/0306 , H05K1/036 , H05K3/4605 , H05K2201/0166 , H05K2201/0175 , H05K2201/10378 , Y10T29/49155 , H01L2924/00
Abstract: PURPOSE: A printed circuit board and a manufacturing method thereof are provided to flatten the surface of a base member by arranging an insulation film layer on the surface of the base member, thereby easily recognizing an alignment key arranged on the base member. CONSTITUTION: A base member(110) is comprised of ceramic or organic materials. An insulation film layer(120) flattens the surface of the base member by being arranged on both surfaces of the base member. A circuit layer(130) is arranged on the insulation film layer. The circuit layer comprises a pad part exposed to the outside and a pad protection layer arranged on the pad part. A via(140) connects the circuit layer arranged on both surfaces of the base member.
Abstract translation: 目的：提供一种印刷电路板及其制造方法，通过在基材的表面上配置绝缘膜层来使基材的表面平坦化，从而容易地识别布置在基材上的对准键。 构成：基体构件（110）由陶瓷或有机材料构成。 绝缘膜层（120）通过布置在基底构件的两个表面上而使基部构件的表面平坦化。 电路层（130）布置在绝缘膜层上。 电路层包括暴露于外部的焊盘部分和布置在焊盘部分上的焊盘保护层。 通孔（140）连接布置在基底构件的两个表面上的电路层。
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公开(公告)号：KR101058637B1
公开(公告)日：2011-08-22
申请号：KR1020090010093
申请日：2009-02-09
Applicant: 삼성전기주식회사
CPC classification number: H01L24/96 , H01L21/568 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/92 , H01L2924/01033 , H01L2924/01059 , H01L2924/01075 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2224/96 , H01L2224/82 , H01L2924/00 , H01L2924/00012
Abstract: 본 발명은 웨이퍼 레벨 패키지의 제조방법에 관한 것으로서, 지지부재 상에 일면에 패드가 구비된 칩을 복수개 실장하는 단계; 상기 칩 사이 공간에 몰딩재를 형성하는 단계; 상기 지지부재를 제거하는 단계; 상기 칩을 포함한 상기 몰딩재의 일면에, 상기 칩의 패드와 접속되는 재분배선을 포함한 절연층을 형성하는 단계; 및 상기 재분배선과 접속되는 외부연결수단을 형성하는 단계;를 포함하는 웨이퍼 레벨 패키지의 제조방법을 제공한다.
웨이퍼 레벨 패키지, 칩, 몰딩-
公开(公告)号：KR1020110028959A
公开(公告)日：2011-03-22
申请号：KR1020090086614
申请日：2009-09-14
Applicant: 삼성전기주식회사
CPC classification number: H01L21/486 , H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L2225/06572 , H01L2924/0002 , H05K3/244 , H05K3/427 , H05K3/4602 , H05K3/4605 , H05K3/4644 , H05K2201/0979 , H05K2201/10378 , H01L2924/00
Abstract: PURPOSE: An interposer using the insulating plate of large size and a manufacture method thereof are provided to reduce the material cost and process expense by manufacturing the interposer using the insulation plate including the resin or the ceramic in stead of silicon wafer. CONSTITUTION: An insulating plate(10) comprises the resin or the ceramics. A first upper redistribution layer(31) is electrically connected to the via(20) according to the circuit pattern designed on the upper side of the insulating plate. A first upper protective layer(41) protects the first upper redistribution layer. A second upper redistribution layer(32) is electrically connected to the first upper redistribution layer.
Abstract translation: 目的：提供使用大尺寸绝缘板的内插器及其制造方法，以通过使用包括树脂或陶瓷的绝缘板代替硅晶片来制造插入件来降低材料成本和工艺成本。 构成：绝缘板（10）包括树脂或陶瓷。 根据设计在绝缘板上侧的电路图案，第一上再分配层（31）与通孔（20）电连接。 第一上保护层（41）保护第一上再分布层。 第二上再分配层（32）电连接到第一上再分配层。
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