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公开(公告)号：KR101474149B1
公开(公告)日：2014-12-17
申请号：KR1020130075758
申请日：2013-06-28
Applicant: 삼성전기주식회사
CPC classification number: H01F38/14 , H01F27/2804 , H01F27/288 , H01F2027/2809 , H02J5/005 , H02J7/025 , H02J50/10 , H02J50/70 , H02J50/80 , Y10T156/1057
Abstract: 본 발명은 복수의 자성체 층을 적층하여 형성되며, 제1면 및 제2면을 가지는 자성 적층체; 상기 제1면의 상부에 형성되는 코일 패턴; 및 상기 코일 패턴의 중심부의 단부에 형성되는 제1 인출부 및 상기 코일 패턴의 외곽에 형성되는 제2 인출부;을 포함하며, 상기 제2면의 일부를 제거하여 공동을 형성하며, 상기 제1 인출부는 상기 공동에 충진되는 도전성 물질과 상기 자성 적층체 내에서 적층방향으로 형성되는 제1 비아에 의해 전기적으로 연결되며, 상기 제2 인출부는 상기 공동에 충진되는 도전성 물질과 상기 자성 적층체에서 적층방향으로 형성되는 제2 비아에 의해 전기적으로 연결되는 것을 특징으로 하는 차폐 부재에 관한 것이다.
Abstract translation: 本发明包括：磁性层叠体，其形成为层叠多个磁性层并具有第一表面和第二表面; 形成在第一表面的上侧的线圈图案; 第一提取单元，其形成在线圈图案的中心的端部; 以及形成在线圈图案的周边区域中的第二提取单元。 本发明涉及通过去除第二表面的一部分而形成空腔的屏蔽构件。 第一提取单元通过在填充在空腔中的导电材料和磁性层叠体中在层叠方向上形成的第一通孔电连接。 第二提取单元通过在填充在空腔中的导电材料和磁性层叠体中在层叠方向上形成的第二通孔电连接。
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公开(公告)号：KR101388756B1
公开(公告)日：2014-05-27
申请号：KR1020120069092
申请日：2012-06-27
Applicant: 삼성전기주식회사
CPC classification number: G02B6/38 , G02B6/3608 , G02B6/4214
Abstract: 본 발명의 실시예에 따른 광 모듈은 기판 상에 실장된 광소자, 및 상기 광소자에 대응하여 상기 광소자의 광신호를 경로변환하여 전달하도록 장착된 광 커넥터를 포함한다.
본 발명에 따른 광 모듈은 제 1 광 커넥터부와 제 2 광 커넥터부가 서로 안정적인 광결합을 이룬 광커넥터를 이용하여 다양한 통신 성능을 갖출 수 있고, 특히 실리콘 광학 벤치(SiOB)를 매개체로 구비하지 않아 제품의 두께를 줄일 수 있으며, 제 1 광 커넥터부에 소정의 경사각으로 구비된 반사판 또는 반사막을 이용하여 광소자의 광신호를 광 화이버로 용이하게 경로 변환할 수 있는 효과가 있다.-
公开(公告)号：KR1020140058135A
公开(公告)日：2014-05-14
申请号：KR1020120124796
申请日：2012-11-06
Applicant: 삼성전기주식회사
IPC: G03F7/20 , H01L21/027
CPC classification number: G03F7/2004 , H01L21/0231 , H01L21/0274
Abstract: The present invention relates to a light exposure apparatus which includes a light exposure unit comprising a light emitting unit emitting ultraviolet rays and a mask with a circuit pattern, and a surface processing unit forming the surface roughness on a substrate by being formed on one side of the light exposure unit. The light exposure apparatus additionally includes a chamber for storing the light exposure unit and the surface processing unit, and a substrate moving unit moving the substrate by being installed inside the chamber.
Abstract translation: 本发明涉及一种曝光装置，该曝光装置包括一个曝光单元，该曝光单元包括一个发射紫外线的发光单元和一个具有电路图案的掩模，以及一个表面处理单元， 曝光单元。 曝光装置还包括用于存储曝光单元和表面处理单元的室，以及通过安装在室内而移动基板的基板移动单元。
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公开(公告)号：KR1020130090234A
公开(公告)日：2013-08-13
申请号：KR1020120011396
申请日：2012-02-03
Applicant: 삼성전기주식회사
CPC classification number: H05K1/115 , H05K1/0251 , H05K3/4644 , H05K2201/09781
Abstract: PURPOSE: A circuit board is provided to control parasitic capacitance existing in the circuit board, by improving loss of capacitance by applying a dummy pattern to the top or bottom of a power via. CONSTITUTION: A circuit board includes a base substrate (110) and an insulation layer (120). The base substrate includes a power via (111) and a power via pad (113). The power via pad is connected to the power via. The insulation layer is formed on the base substrate, and includes a dummy pattern (115) formed in an area facing with the power via pad.
Abstract translation: 目的：提供电路板来控制存在于电路板中的寄生电容，通过将虚拟图案应用于电源通孔的顶部或底部来改善电容损耗。 构成：电路板包括基底（110）和绝缘层（120）。 基底基板包括电源通孔（111）和电源通孔垫（113）。 电源通孔焊盘连接到电源通孔。 绝缘层形成在基底基板上，并且包括形成在与电源通孔焊盘相对的区域中的虚拟图案（115）。
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公开(公告)号：KR1020130054769A
公开(公告)日：2013-05-27
申请号：KR1020110120353
申请日：2011-11-17
Applicant: 삼성전기주식회사
CPC classification number: H01L23/49827 , H01L23/49838 , H01L2224/16225 , H01L2224/73265
Abstract: PURPOSE: A semiconductor package and a semiconductor package module having the same are provided to reduce the number of processes by forming an open type pattern in one layer. CONSTITUTION: A semiconductor chip(110) has a bonding pad. A first substrate(150) is electrically connected to the bonding pad. The first substrate has a redistribution layer(140) and a signal connection terminal(1D,2D). The redistribution layer includes a short type redistribution pattern(B) and an open type redistribution pattern(A). The signal connection terminal is formed in the open type redistribution pattern.
Abstract translation: 目的：提供具有该半导体封装和半导体封装模块的半导体封装模块，以通过在一层中形成开放型图案来减少工艺数量。 构成：半导体芯片（110）具有接合焊盘。 第一基板（150）电连接到接合焊盘。 第一衬底具有再分配层（140）和信号连接端子（1D，2D）。 再分配层包括短型重新分配模式（B）和开放式再分配模式（A）。 信号连接端子形成为开放型再分布图案。
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Patent Agency Ranking
公开(公告)号：KR1020130047589A
公开(公告)日：2013-05-08
申请号：KR1020120117043
申请日：2012-10-22
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A high density asymmetry multilayer substrate having an odd number pattern layer of a simple asymmetric structure, an RF module, and an asymmetry multilayer substrate manufacturing method are provided to enable a low cost design and manufacturing by improving the impedance transformation of the inter-layer interconnection. CONSTITUTION: An asymmetry multilayer substrate is comprised of the followings: a core layer(20) which penetrates and connects the upper and lower part and forms a through-hole; a first pattern layer(10) which is formed on the upper part or lower part of the core layer, and includes a first signal line pattern which is connected to the through-hole; a second pattern layer(30) which is formed in the other upper or lower part of the core layer, and includes a second metal plate which provides the capacitance between a second path pattern connected to the through-hole and a pattern of an adjacent outline pattern layer; a first insulation layer(40) which is formed in a thickness less than the thickness of the core layer on a second pattern layer, and forms a first VIA which is connected to the second path pattern; and a third pattern layer(50) which is formed on the first insulation layer, and includes a third signal line pattern which is connected to the first VIA. An impedance conversion circuit is formed which includes an impedance loading on a transmission line or a parasitic capacitance load on the transmission line for the impedance matching in the signal transmission between the signal line patterns which are formed in the up and down direction of the core layer. The impedance load includes a through-hole which comprises the transmission line, the second path pattern, and the impedance of the first VIA. The parasitic capacitance load includes the capacitance provided with the second metal plate.
Abstract translation: 目的：提供具有简单不对称结构的奇数图案层，RF模块和不对称多层基板制造方法的高密度不对称多层基板，以通过改进相互间的不对称的多层基板的阻抗变换来实现低成本的设计和制造， 层互连。 构成：不对称多层基板由以下部分组成：芯层（20）穿透并连接上部和下部并形成通孔; 第一图案层（10），其形成在所述芯层的上部或下部，并且包括连接到所述通孔的第一信号线图案; 第二图案层（30），形成在芯层的另一个上部或下部，并且包括第二金属板，其在连接到通孔的第二路径图案和相邻轮廓的图案之间提供电容 图案层; 第一绝缘层（40），其形成为厚度小于第二图案层上的芯层的厚度，并且形成连接到第二路径图案的第一VIA; 以及第三图案层（50），其形成在所述第一绝缘层上，并且包括连接到所述第一VIA的第三信号线图案。 形成阻抗转换电路，其包括在传输线上的阻抗负载或传输线上的寄生电容负载，用于在芯层的上下方向上形成的信号线图案之间的信号传输中的阻抗匹配 。 阻抗负载包括通孔，该通孔包括传输线，第二路径图案和第一VIA的阻抗。 寄生电容负载包括设置有第二金属板的电容。
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公开(公告)号：KR101179386B1
公开(公告)日：2012-09-03
申请号：KR1020100032244
申请日：2010-04-08
Applicant: 삼성전기주식회사 , 성균관대학교산학협력단
CPC classification number: H01L21/50 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L2224/131 , H01L2224/16146 , H01L2224/16235 , H01L2924/0001 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/19015 , H01L2924/19041 , Y10T436/170769 , H01L2224/13099
Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.
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公开(公告)号：KR101113501B1
公开(公告)日：2012-02-29
申请号：KR1020090109027
申请日：2009-11-12
Applicant: 삼성전기주식회사
IPC: H01L23/48
CPC classification number: H01L23/5389 , H01L23/49827 , H01L24/24 , H01L24/82 , H01L2224/0231 , H01L2224/24226 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H05K1/185 , H05K2201/10674 , H05K2203/1469 , H01L2924/00
Abstract: 본 발명에 따른 반도체 패키지의 제조 방법은 기판 웨이퍼 상에 절연층을 형성시키는 단계; 상기 절연층 상에 회로 연결을 하도록 재배선 도금하여 전극 패턴부를 형성시키는 단계; 상기 재배선 도금이 일부 노출되도록 상기 재배선 도금 상부에 보호부를 형성시켜 반도체 칩을 제조하는 단계; 및 내측에 수용 공간이 형성된 회로 기판에 상기 반도체 칩을 실장하여 전기적으로 연결하는 단계;를 포함할 수 있다.
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公开(公告)号：KR1020110112974A
公开(公告)日：2011-10-14
申请号：KR1020100032244
申请日：2010-04-08
Applicant: 삼성전기주식회사 , 성균관대학교산학협력단
CPC classification number: H01L21/50 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L2224/131 , H01L2224/16146 , H01L2224/16235 , H01L2924/0001 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/19015 , H01L2924/19041 , Y10T436/170769 , H01L2224/13099
Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.
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公开(公告)号：KR101060936B1
公开(公告)日：2011-08-30
申请号：KR1020100004850
申请日：2010-01-19
Applicant: 삼성전기주식회사
CPC classification number: H05K3/32 , H01L23/13 , H01L23/49805 , H01L2924/0002 , H05K2201/09145 , H05K2201/09154 , H05K2201/10378 , H05K2201/10674 , H01L2924/00
Abstract: 본 발명에 따른 인터커넥션 구조는 기판부의 측면에 형성되는 복수개의 측면부 및, 상기 측면부들 사이에 위치하며 상기 측면부들보다 내측에 위치하도록 형성되는 복수개의 캐비티; 및 상기 측면부 및 상기 캐비티의 표면에 형성되는 전극 패턴부;를 포함할 수 있다.
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