公开(公告)号：KR101638976B1

公开(公告)日：2016-07-13

申请号：KR1020100082645

申请日：2010-08-25

Applicant: 삼성전자주식회사

Inventor： 김호정 ,  신재광 ,  최현식

IPC: G11C16/06 ,  G11C16/10

CPC classification number: H03K19/17752 ,  H03K19/17756

Abstract: 본발명은재구성가능한논리장치에관한것으로, 제1 논리블록및 제2 논리블록을포함하는적어도두 개의논리블록들, 상기제1 논리블록에연결되는복수의제1 글로벌배선들과상기제2 논리블록에연결되는복수의제2 글로벌배선들을포함하는글로벌배선그룹, 및상기복수의제1 글로벌배선들과상기복수의제2 글로벌배선들이교차하는영역들에각각배치되는복수의제1 비휘발성메모리소자들을포함하고, 상기논리장치의동작을실시간으로재구성하기위하여상기복수의제1 비휘발성메모리소자들각각에저장된제1 데이터를기초로하여상기복수의제1 및제2 글로벌배선들의라우팅을제어하는글로벌제어부를포함한다.

公开(公告)号：KR101632314B1

公开(公告)日：2016-06-22

申请号：KR1020090085874

申请日：2009-09-11

Applicant: 삼성전자주식회사

Inventor： 홍기하 ,  김종섭 ,  오재준 ,  신재광 ,  최혁순 ,  황인준 ,  김호정

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

Abstract: 전계효과형반도체소자에대해개시된다. 개시된전자효과형반도체소자는 2DEG가형성되며이종접합구조의반도체층들을포함하며, 게이트전극을소스및 드레인과서로다른면에형성함으로써전기적특성을향상시킨전계효과형반도체소자를제공한다.

公开(公告)号：KR101615635B1

公开(公告)日：2016-05-13

申请号：KR1020100022948

申请日：2010-03-15

Applicant: 삼성전자주식회사

Inventor： 김호정 ,  신재광 ,  오재준 ,  김종섭 ,  최혁순 ,  황인준 ,  홍기하

IPC: H03K17/30 ,  H03K17/687

CPC classification number: H03K17/6871 ,  H02M1/08 ,  H02M3/158 ,  H02M3/337 ,  H02M2001/0074 ,  H03K2217/0081

Abstract: 본발명은반도체장치에관한것으로, 음의문턱전압(threshold voltage)을가지는스위칭소자, 및전원단자와접지단자사이에연결되어, 스위칭소자를구동하기위한구동전압을제공하는구동부를포함하고, 스위칭소자는, 접지단자에서공급되는접지전압보다높은가상접지전압을가지는가상접지노드(node)에연결되어, 구동전압과가상접지전압의차이가상기문턱전압보다큰 경우에온(on)된다.

公开(公告)号：KR1020130113204A

公开(公告)日：2013-10-15

申请号：KR1020120035598

申请日：2012-04-05

Applicant: 삼성전자주식회사

Inventor： 최현식 ,  김호정 ,  신재광 ,  정우인

IPC: H03K17/687 ,  H02M1/08

CPC classification number: H03K3/00 ,  G05F3/02 ,  H01L2924/0002 ,  H03K17/06 ,  H01L2924/00

Abstract: PURPOSE: A high side gate driver, a switching chip, and a power device thereof are provided to prevent a destruction phenomenon generated by applying a high voltage to switching elements. CONSTITUTION: A high side gate driver (HGD) comprises a first low level driving power source, a protection element, and a first switching element (SW1). The first low level driving power source turns on a high side normally-on switch (HS). The production device and the first switching device serially connect the first low level driving power source to the gate of the high side normally-on switch. The protection element includes an additional normally-on switch. The additional normally-on switch increases the voltages applied to the gate and reduces the surface of the high side normally-on switch.

Abstract translation: 目的：提供高侧栅极驱动器，开关芯片及其功率器件，以防止对开关元件施加高电压而产生的破坏现象。 构成：高侧栅极驱动器（HGD）包括第一低电平驱动电源，保护元件和第一开关元件（SW1）。 第一个低电平驱动电源打开高边正常开关（HS）。 生产装置和第一开关装置将第一低电平驱动电源串联连接到高侧常开开关的栅极。 保护元件包括一个额外的常开开关。 额外的常开开关增加了施加到栅极的电压并降低了高边常开开关的表面。

公开(公告)号：KR1020130104584A

公开(公告)日：2013-09-25

申请号：KR1020120026201

申请日：2012-03-14

Applicant: 삼성전자주식회사

Inventor： 김호정 ,  신재광 ,  정우인 ,  최현식

IPC: H02H9/00 ,  H01L23/62 ,  H02M1/32

CPC classification number: H02H9/02 ,  H01L2924/0002 ,  H03K17/165 ,  H03K17/56 ,  H03K2217/0036 ,  H01L2924/00

Abstract: PURPOSE: A power module with a leakage current protection circuit increases the reliability of an operation by maintaining the stable operation of a power device and a module. CONSTITUTION: An input terminal of a leakage current protection circuit is connected to a power device. An output terminal of the leakage current protection circuit is connected to a control block (22). Multiple PMOS transistors (30) are connected to multiple NMOS transistors (28). An input terminal of a comparator is connected to a connection wire between the NMOS transistor and the PMOS transistor. An output terminal of the comparator is connected to the control block.

Abstract translation: 目的：具有漏电流保护电路的电源模块通过维持电源设备和模块的稳定运行来提高操作的可靠性。 构成：泄漏电流保护电路的输入端子连接到电源装置。 泄漏电流保护电路的输出端子连接到控制块（22）。 多个PMOS晶体管（30）连接到多个NMOS晶体管（28）。 比较器的输入端子连接到NMOS晶体管和PMOS晶体管之间的连接线。 比较器的输出端子连接到控制块。

公开(公告)号：KR1020130030103A

公开(公告)日：2013-03-26

申请号：KR1020110093646

申请日：2011-09-16

Applicant: 삼성전자주식회사

Inventor： 김호정 ,  정우인 ,  신재광

IPC: G11C29/00 ,  G01R19/175

CPC classification number: H01L29/78684 ,  G11C29/12005 ,  G11C29/00 ,  G01R19/175

Abstract: PURPOSE: A semiconductor device and an operating method thereof are provided to prevent malfunction of a graphene transistor by detecting a Dirac point. CONSTITUTION: A voltage generator generates a test voltage. A graphene transistor(GTr) receives a gate-source voltage based on the test voltage. A detector(DTEC) detects whether the gate-source voltage is a Dirac voltage of the graphene transistor and outputs a feedback signal to show whether the gate-source voltage is the Dirac voltage of the graphene transistor. The feedback signal is applied to the voltage generator.

Abstract translation: 目的：提供一种半导体器件及其操作方法，以通过检测狄拉克点来防止石墨烯晶体管的故障。 构成：电压发生器产生测试电压。 石墨烯晶体管（GTr）基于测试电压接收栅极 - 源极电压。 检测器（DTEC）检测栅极 - 源极电压是否是石墨烯晶体管的狄拉克电压，并且输出反馈信号以显示栅极 - 源极电压是否为石墨烯晶体管的狄拉克电压。 反馈信号被施加到电压发生器。

公开(公告)号：KR1020120063165A

公开(公告)日：2012-06-15

申请号：KR1020100124234

申请日：2010-12-07

Applicant: 삼성전자주식회사

Inventor： 김호정 ,  신재광 ,  최현식 ,  정형수

IPC: G11C7/06 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08 ,  G11C7/04 ,  G11C11/56 ,  G11C13/00

CPC classification number: G11C7/12 ,  G11C7/04 ,  G11C7/062 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0016 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/004 ,  G11C2207/002 ,  G11C7/06 ,  G11C5/14 ,  G11C8/08

Abstract: PURPOSE: A semiconductor device and a data sensing method thereof are provided to reduce an area of the semiconductor device by sensing data stored in a memory cell without an additional reference cell. CONSTITUTION: A memory cell array(10) includes a memory cell arranged at an intersection between a bit line and a word line. A sensing unit(40) senses the data stored in the memory cell. A connection control unit(41) controls a connection between a bit line and a sensing line based on a voltage level of the bit line and a control signal with a variable voltage level. A sense amplifier(43) senses data stored in the memory cell by comparing the voltage of the sensing line with the reference voltage.

Abstract translation: 目的：提供一种半导体器件及其数据感测方法，以通过感测存储在存储单元中的数据来减少半导体器件的面积，而不需要额外的参考单元。 构成：存储单元阵列（10）包括布置在位线和字线之间的交叉点处的存储单元。 感测单元（40）感测存储在存储单元中的数据。 连接控制单元（41）基于位线的电压电平和具有可变电压电平的控制信号来控制位线和感测线之间的连接。 感测放大器（43）通过将感测线的电压与参考电压进行比较来感测存储单元中存储的数据。

公开(公告)号：KR1020120028166A

公开(公告)日：2012-03-22

申请号：KR1020100090218

申请日：2010-09-14

Applicant: 삼성전자주식회사

Inventor： 김호정 ,  강상범 ,  황홍선 ,  박철우

IPC: G11C11/401 ,  G11C13/00 ,  G11C29/02 ,  G11C11/406

CPC classification number: G11C29/021 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C16/3418 ,  G11C2013/0057 ,  G11C2013/0076 ,  G11C11/401 ,  G11C11/406

Abstract: PURPOSE: A resistive memory apparatus and a refreshing control method thereof are provided to improve data reliability by periodically and/or aperiodically determining a refresh entry time. CONSTITUTION: A refresh reading process is performed in order to check a state of a plurality of memory units(S11). A refresh entry state is determined with respect to each memory unit according to a data result read through the refresh reading process(S12). A refresh process is performed with respect to the memory unit which requires the refresh process according to a determined result(S13). A standard of the refresh reading process has a small margin of read data distribution compared to a standard of a normal reading process. A memory cell array is classified into a plurality of memory blocks. Each memory block is classified into a plurality of memory pages.

Abstract translation: 目的：提供一种电阻式存储装置及其刷新控制方法，通过周期地和/或不定期地确定刷新入口时间来提高数据的可靠性。 构成：执行刷新读取处理以检查多个存储单元的状态（S11）。 根据通过刷新读取处理读取的数据结果，相对于每个存储器单元确定刷新输入状态（S12）。 相对于根据确定结果需要刷新处理的存储器单元执行刷新处理（S13）。 刷新读取过程的标准与正常读取过程的标准相比具有小的读取数据分布。 存储单元阵列分为多个存储块。 每个存储块被分类成多个存储器页。

公开(公告)号：KR1020120012892A

公开(公告)日：2012-02-13

申请号：KR1020100074983

申请日：2010-08-03

Applicant: 삼성전자주식회사

Inventor： 최현식 ,  김호정

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/10 ,  G11C16/06

CPC classification number: G11C16/34 ,  G11C16/06 ,  G11C16/10 ,  G11C16/32

Abstract: PURPOSE: A lookup table circuit is provided to remove a reconfiguration set for a logic operation by storing the logic operation using a nonvolatile memory device even though power is off. CONSTITUTION: A first path unit(110) includes a first input terminal. The first input terminal receives a first bit signal. The first bit signal includes a first configuration bit and a first read bit. The first path unit electrically connects a first node to a second node or a third node. A second path unit(120) includes a second input terminal and a third input terminal. The second input terminal and the third input terminal include a second configuration bit and a second read bit. The second path unit connects a second node to a fourth node or a fifth node. The second path unit connects a third node to a sixth node or a seventh node. A logic operation circuit includes first to fourth nonvolatile memory devices(141,143,145,147) which are programmable.

Abstract translation: 目的：提供查找表电路以通过使用非易失性存储器件存储逻辑操作即使电源关闭来去除用于逻辑操作的重新配置集合。 构成：第一路径单元（110）包括第一输入端。 第一输入端接收第一位信号。 第一位信号包括第一配置位和第一读位。 第一路径单元将第一节点电连接到第二节点或第三节点。 第二路径单元（120）包括第二输入端和第三输入端。 第二输入端子和第三输入端子包括第二配置位和第二读位。 第二路径单元将第二节点连接到第四节点或第五节点。 第二路径单元将第三节点连接到第六节点或第七节点。 逻辑运算电路包括可编程的第一至第四非易失性存储器件（141,143,145,147）。

公开(公告)号：KR1020110128640A

公开(公告)日：2011-11-30

申请号：KR1020100048187

申请日：2010-05-24

Applicant: 삼성전자주식회사

Inventor： 전상훈 ,  김호정

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11551 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926 ,  H01L27/0207

Abstract: PURPOSE: A laminate memory device and a manufacturing method thereof are provided to improve the degree of integration of a memory device by laminating a peripheral circuit in the top or bottom side of a memory. CONSTITUTION: A laminate memory device comprises one memory unit(121) and one peripheral circuit unit. The one peripheral circuit unit is formed in one of top and bottom side of the memory unit. A memory string array is perpendicularly formed on a substrate and has a plurality of memory strings which is arranged into a matrix type. Each of a plurality of memory strings comprises a plurality of memory cells and a string select device. A plurality of bit lines(BL0-BL7) is connected to each one end of a plurality of memory strings and is extended to a first direction. A plurality of string select pads(SSP0-SSP3) is connected to the string select devices which are included in a plurality of memory strings and is arranged according to the first direction.

Abstract translation: 目的：提供层压存储器件及其制造方法，以通过将外围电路层压在存储器的顶部或底部来提高存储器件的集成度。 构成：层压存储装置包括一个存储单元（121）和一个外围电路单元。 一个外围电路单元形成在存储单元的顶侧和底侧之一中。 存储器串阵列垂直地形成在衬底上并且具有排列成矩阵型的多个存储器串。 多个存储器串中的每一个包括多个存储器单元和一个串选择装置。 多个位线（BL0-BL7）连接到多个存储器串的每一端并被延伸到第一方向。 多个串选择焊盘（SSP0-SSP3）连接到包含在多个存储器串中的串选择装置，并且根据第一方向布置。