中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

62 records (took 0.018 seconds)

    반도체 메모리 어레이의 워드라인 배열방법
    11.
    发明授权
    반도체 메모리 어레이의 워드라인 배열방법 失效
    半导体存储器装置的WORDLINE阵列方法

    公开(公告)号：KR1019930001737B1

    公开(公告)日：1993-03-12

    申请号：KR1019890020102

    申请日：1989-12-29

    Applicant: 삼성전자주식회사

    Inventor： 민동선 ,  조수인 ,  진대제

    IPC: G11C11/34

    CPC classification number: H01L23/5222 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The arranging method comprises twisting word lines in groups of four so that lines which are adjancent over part of their length become non-adjacent over another part of their length and arranging the word lines so as to reduce the coupling capacitances between the lines. A group of four word lines are assigned to each word line driver, and each line is twisted with at least one other line of the same group. The method decreases the coupling noise between the word lines. The semiconductor memory array comprises a number of memory cells, a number of bit lines (BL), a number of word lines (WL) and sense amplifiers (SA).

    Abstract translation: 排列方法包括以四组的方式扭转字线，使得在其长度的一部分上相邻的线在其长度的另一部分上不相邻并且布置字线以便减小线之间的耦合电容。 一组四个字线被分配给每个字线驱动器，并且每条线与同一组的至少另一条线扭曲。 该方法降低了字线之间的耦合噪声。 半导体存储器阵列包括多个存储单元，多个位线（BL），多个字线（WL）和读出放大器（SA）。

    반도체 집적소자의 내부전압 변환회로
    12.
    发明授权
    반도체 집적소자의 내부전압 변환회로 失效
    半导体集成器件的内部电压转换电路

    公开(公告)号：KR1019920010749B1

    公开(公告)日：1992-12-14

    申请号：KR1019890008067

    申请日：1989-06-10

    Applicant: 삼성전자주식회사

    Inventor： 민동선

    IPC: G11C17/00

    CPC classification number: H03K17/063 ,  G05F1/465 ,  G05F1/59 ,  G11C5/145 ,  G11C5/147 ,  H02M3/07 ,  H02M3/073 ,  H03K17/302 ,  H03K17/6871 ,  H03K2217/0036

    Abstract: The converter circuit has a number of parallel-connected internal voltage converting stages to reduce the power consumption in case of providing the stand-by power and to improve the stability of the internal supply voltage, each stages (10,20) including a buffer (2,2'), a charge pumping unit (3,3') and a power unit (4,4'). The convert circuit comprises an oscillator (1) for generating square waves, a sub-curcuit (10), a main circuit (20) and a detector (5) for detecting the insternal power supply voltage to control the operation of the buffer (2'). The power unit controls the level of the internal supply voltage by the charge pumping unit. In a stand-by mode, only the sub-circuit (10) operates.

    Abstract translation: 转换器电路具有多个并联连接的内部电压转换级，以在提供待机功率的情况下降低功耗并提高内部电源电压的稳定性，每个级（10,20）包括缓冲器 2,2'），电荷泵送单元（3,3'）和动力单元（4,4'）。 转换电路包括用于产生方波的振荡器（1），副电路（10），主电路（20）和检测器（5），用于检测本征电源电压以控制缓冲器（2）的操作 “）。 电源单元通过电荷泵送单元控制内部电源电压的电平。 在待机模式中，只有子电路（10）工作。

    백바이어스전압발생회로
    14.
    发明授权
    백바이어스전압발생회로 失效
    返回偏置电压发生电路

    公开(公告)号：KR1019910009556B1

    公开(公告)日：1991-11-21

    申请号：KR1019890006333

    申请日：1989-05-11

    Applicant: 삼성전자주식회사

    Inventor： 민동선

    IPC: G11C11/40

    Abstract: The circuit generates the stable back-bias voltage. A 1st buffer (21) and the 1st charge pumper (31) continue operating regardless of the back-bias voltage. A 2nd buffer (22) and a 2nd charge pumper (32) receives the outputs of an oscillator (10) and a voltage-level detector (40) simultaneously. When the back-bias voltage is varied according to the noise, the 2nd buffer (22) and the 2nd charge pumper (32) start operating to stabilize the level of the back-bias voltage.

    Abstract translation: 该电路产生稳定的背偏电压。 无论背偏压如何，第一缓冲器（21）和第一电荷泵（31）继续运行。 第二缓冲器（22）和第二电荷泵（32）同时接收振荡器（10）和电压电平检测器（40）的输出。 当背偏电压根据噪声变化时，第二缓冲器（22）和第二电荷泵（32）开始运行，以稳定背偏电压的电平。

Patent Agency Ranking