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公开(公告)号：KR1020140111758A
公开(公告)日：2014-09-22
申请号：KR1020130026036
申请日：2013-03-12
Applicant: 삼성전자주식회사
CPC classification number: H04N5/23241 , H04N5/23206 , H04N5/23245 , H04N5/378 , H04N9/045
Abstract: An image processing device includes a pixel array and a data processing part. The pixel array includes multiple unit pixels which generate multiple color signals in response to incident light, respectively. The data processing part generates output image data by processing the color signals in parallel in a first operating mode; generates two image signals for each of the unit pixels, based on the color signals in a second operating mode; and generates output image data by processing the two image signals in parallel. The image processing device can operate in a high quality image taking mode and a power saving mode according to the selection of a user.
Abstract translation: 图像处理装置包括像素阵列和数据处理部。 像素阵列包括分别响应于入射光产生多个颜色信号的多个单位像素。 数据处理部分通过在第一操作模式中并行处理彩色信号来产生输出图像数据; 基于第二操作模式中的颜色信号，为每个单位像素生成两个图像信号; 并且通过并行处理两个图像信号来产生输出图像数据。 图像处理装置可以根据用户的选择以高质量的图像拍摄模式和省电模式进行操作。
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公开(公告)号：KR1020140046862A
公开(公告)日：2014-04-21
申请号：KR1020120113042
申请日：2012-10-11
Applicant: 삼성전자주식회사
CPC classification number: A61B6/4452 , A61B6/4435 , A61B6/5241
Abstract: Disclosed is an X-ray photographing device comprising: a source for emitting X-rays to a target object; a detector for detecting the X-rays penetrating the target object; an arm for connecting the source and the detector, and vertically moving the detector according to the rotation of the source; a support part for supporting the arm; and a control part for controlling the photographing of the target object by operating the arm. [Reference numerals] (560) Control part
Abstract translation: 公开了一种X射线摄影装置，包括：用于向目标物体发射X射线的源; 用于检测穿透所述目标物体的X射线的检测器; 用于连接源和检测器的臂，以及根据源的旋转垂直移动检测器; 用于支撑臂的支撑部分; 以及用于通过操作所述臂来控制所述目标物体的拍摄的控制部。 （附图标记）（560）控制部
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3.发明公开부호분할 다중접속 방식의 고속 패킷 데이터 시스템에서 다중 안테나를 이용하는 단말의 결합 방식에 따른 가중치의 동적 영역 제어 장치 및 방법 有权动态范围控制装置和与高速分组数据系统中多个天线设备的移动站中组合公式相关的重量矢量方法
公开(公告)号：KR1020070078332A
公开(公告)日：2007-07-31
申请号：KR1020060008551
申请日：2006-01-26
Applicant: 삼성전자주식회사
IPC: H04B7/02
CPC classification number: H04B1/712 , H04B7/0848 , H04B2201/70706 , H04B2201/7071 , H04L25/0206 , H04L25/0212
Abstract: An apparatus and a method for controlling a dynamic range of a weight according to a combining formula of a terminal using multiple antennas in a high speed packet data system of CDMA are provided to control a dynamic range of a weight multiplied to a PN-descrambled signal in a mobile terminal. A channel estimator(202) receives a pilot symbol transmitted from a base station and calculates a channel estimated value of a reception path of each antenna. An autocorrelation matrix calculator(204) calculates an autocorrelation matrix value at every chip interval determined from the received pilot symbol. A weight vector calculator(206) calculates a corresponding weight vector by using the channel estimated value and/or autocorrelation matrix value according to a combining method selected according to a channel environment. A controller(208) determines whether to correct the weight vector according to the selected combining method, and when the weight vector needs to be corrected, the controller outputs a corrected weight vector by using a scale factor. A combiner(210) outputs a combining signal by multiplying the weight vector outputted from the controller to a descrambled signal.
Abstract translation: 提供了一种用于根据在CDMA的高速分组数据系统中使用多个天线的终端的组合公式来控制权重的动态范围的装置和方法，以控制与PN解扰信号相乘的权重的动态范围 在移动终端。 信道估计器（202）接收从基站发送的导频符号，并计算每个天线的接收路径的信道估计值。 自相关矩阵计算器（204）根据从接收到的导频符号确定的每个码片间隔计算自相关矩阵值。 权重向量计算器（206）根据根据信道环境选择的组合方法，使用信道估计值和/或自相关矩阵值来计算对应的权重向量。 控制器（208）根据选择的组合方法确定是否校正权重向量，并且当需要校正权重向量时，控制器通过使用比例因子输出校正的权重向量。 组合器（210）通过将从控制器输出的加权矢量乘以解扰信号来输出组合信号。
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公开(公告)号：KR100104792B1
公开(公告)日：1996-09-13
申请号：KR1019930003739
申请日：1993-03-12
Applicant: 삼성전자주식회사
IPC: G11C11/407
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公开(公告)号：KR1019940009247B1
公开(公告)日：1994-10-01
申请号：KR1019910013272
申请日：1991-07-31
Applicant: 삼성전자주식회사
IPC: G11C11/407
Abstract: The address buffer for a flash write mode in a semiconductor memory device includes a logic circuit for inputting a flash write signal and a column address latch signal respectively, and cutting off a transmission of the inside address to an output node by making a transmission operation of a transmitting gate operate-off; and a pull-up circuit formed between a given supply voltage terminal and the output node, for gate-inputting the flash write signal and supplying the supply voltage synchronizing to an activation input of the flash write signal to the ouput node.
Abstract translation: 用于半导体存储器件中闪速写入模式的地址缓冲器包括分别输入闪速写入信号和列地址锁存信号的逻辑电路，并且通过进行发送操作来切断内部地址到输出节点的传输 发射门操作; 以及形成在给定电源电压端子和输出节点之间的上拉电路，用于对闪存写入信号进行栅极输入，并将与Flash写入信号的激活输入同步的电源电压提供给输出节点。
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Patent Agency Ranking
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公开(公告)号：KR1019930003145A
公开(公告)日：1993-02-23
申请号：KR1019910013272
申请日：1991-07-31
Applicant: 삼성전자주식회사
IPC: G11C11/407
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公开(公告)号：KR100054960B1
公开(公告)日：1992-09-28
申请号：KR1019890011700
申请日：1989-08-17
Applicant: 삼성전자주식회사
Inventor： 이동재
IPC: H03K3/00 , G11C11/407
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公开(公告)号：KR1019920008759A
公开(公告)日：1992-05-28
申请号：KR1019900016458
申请日：1990-10-15
Applicant: 삼성전자주식회사
IPC: G11C11/409
Abstract: 내용 없음.
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