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公开(公告)号：KR1020160034550A
公开(公告)日：2016-03-30
申请号：KR1020140125437
申请日：2014-09-22
Applicant: 삼성전자주식회사
CPC classification number: H03K19/0005 , H03K19/0013
Abstract: 스토리지컨트롤러는제1 온-다이터미네이션(on-die termination, 이하 ODT) 회로, 제2 ODT 회로및 ODT 제어회로를포함한다. 상기제1 ODT 회로는데이터스트로브신호가전달되는스트로브신호라인에제1 종단저항을제공한다. 상기제2 ODT 제어회로는데이터가전달되는적어도하나의데이터라인에제2 종단저항을제공한다. 상기 ODT 제어회로는상기제1 ODT 회로와상기제2 ODT 회로의활성화와비활성화를개별적으로제어한다.
Abstract translation: 本发明提供一种能够降低功耗的存储控制器。 存储控制器包括：向接收数据选通信号的选通信号线提供第一终端电阻的第一管芯内端子（ODT）电路; 向接收数据的至少一个数据线提供第二终端电阻的第二ODT电路; 以及分别控制第一ODT电路和第二ODT电路的激活和去激活的ODT控制电路。
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公开(公告)号：KR1020130092110A
公开(公告)日：2013-08-20
申请号：KR1020120013623
申请日：2012-02-10
Applicant: 삼성전자주식회사
Inventor： 박광수
CPC classification number: G11C16/04 , G06F3/0607 , G06F3/0626 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F12/0246 , G11C5/04 , G11C16/30 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00
Abstract: PURPOSE: An embedded solid-state disk (eSSD) and a solid-state disk (SSD) are provided to reduce production cost by eliminating the need of a separate process to produce a controller. CONSTITUTION: Non-volatile memory devices (342-34n) store data, and an eSSD (400) controls the non-volatile memory devices. The eSSD includes a first layer containing control logic and a second layer which is laminated on the upper part of the first layer and contains a non-volatile memory. The second layer includes a volatile memory temporarily storing data. The eSSD includes non-volatile memory interfaces performing interfacing operations with the non-volatile memory devices.
Abstract translation: 目的：提供嵌入式固态磁盘（eSSD）和固态磁盘（SSD），以减少生产成本，不需要单独的过程来生产控制器。 规定：非易失性存储设备（342-34n）存储数据，eSSD（400）控制非易失性存储设备。 eSSD包括包含控制逻辑的第一层和层叠在第一层的上部并且包含非易失性存储器的第二层。 第二层包括临时存储数据的易失性存储器。 eSSD包括与非易失性存储器件执行接口操作的非易失性存储器接口。
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公开(公告)号：KR1020090070226A
公开(公告)日：2009-07-01
申请号：KR1020070138154
申请日：2007-12-27
Applicant: 삼성전자주식회사
IPC: G11C7/10
CPC classification number: G11C7/10 , G11C5/06 , G11C11/401
Abstract: A layout structure of receivers and transmission lines is provided to reduce a difference of loading capacitance and a difference of a signal delay between receiver groups. A first receiver group and a second receiver group include a plurality of receivers. A plurality of receivers is connected through a first fixing transmission line to an eighth fixing transmission line(T1~T8). The second receiver group additionally includes a first variable transmission line to an eighth variable transmission line(T11~T88). The variable transmission lines are parallel arranged in the fixing transmission lines. The variable transmission lines have the same or different impedance as the fixing transmission lines. The variable transmission lines are arranged on the same or different wiring layer as the fixing transmission lines.
Abstract translation: 提供接收机和传输线的布局结构，以减少负载电容的差异和接收器组之间的信号延迟差。 第一接收机组和第二接收机组包括多个接收机。 多个接收器通过第一固定传输线连接到第八固定传输线（T1〜T8）。 第二接收机组另外包括到第八可变传输线（T11〜T88）的第一可变传输线。 可变传输线平行布置在固定传输线中。 可变传输线具有与固定传输线相同或不同的阻抗。 可变传输线布置在与固定传输线相同或不同的布线层上。
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Patent Agency Ranking
公开(公告)号：KR100744130B1
公开(公告)日：2007-08-01
申请号：KR1020060016227
申请日：2006-02-20
Applicant: 삼성전자주식회사
IPC: G11C11/4093
Abstract: A termination circuit and a semiconductor memory device comprising the same are provided to improve problems due to the increase of power consumption by periodically controlling whether to enable the termination circuit when a data signal is input. In a termination circuit connected to an input buffer(110) receiving a data signal, at least one termination resistor is connected to the input buffer for impedance matching. At least one switch part controls the connection between the input buffer and the termination resistor. A control signal generation part(140) generates a control signal to control on/off of the switch part. The control signal generation part generates a control signal having a period of 1/n of the data signal input period, and controls the termination circuit to be enabled in a partial period of the data signal input period.
Abstract translation: 提供了一种端接电路和包括该端接电路的半导体存储器件，以通过在输入数据信号时周期性地控制是否使能端接电路来改善由于功耗的增加而导致的问题。 在连接到接收数据信号的输入缓冲器（110）的终端电路中，至少一个终端电阻器连接到输入缓冲器用于阻抗匹配。 至少有一个开关部分控制输入缓冲器和终端电阻之间的连接。 控制信号生成部（140）生成用于控制开关部的接通/断开的控制信号。 控制信号产生部分产生周期为数据信号输入周期的1 / n的控制信号，并且控制终止电路在数据信号输入周期的部分周期中被使能。
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公开(公告)号：KR1020070069586A
公开(公告)日：2007-07-03
申请号：KR1020050131887
申请日：2005-12-28
Applicant: 삼성전자주식회사
IPC: H04L29/02
CPC classification number: H04L25/0272
Abstract: A double differential transmission method and a double differential transmission apparatus are provided to transmit plural signals in a restricted area by transmitting a differential signal between transmission lines. A data transmission system includes first to third transmission lines(311,313,315) and transmits 2-bit data. The first to third transmission lines transmit each of the first to third voltage signals which have one of the voltage levels of first to third voltage levels, so that first and second electric fields have different logic combinations according to logic state of the 2 bit data. The first electric field is generated between the first and second transmission lines. The second electric field is generated between the second and third transmission lines. The transmission system includes a driving unit(410) and a receiving unit(470). The driving unit generates the first to third voltage signals in response to the 2-bit data and transmits the first to third voltage signals to the first to third transmission lines. The receiving unit receives the first to third voltage signals and generates the 2-bit data.
Abstract translation: 提供双差分传输方法和双差分传输装置，通过在传输线之间传送差分信号来在限制区域中传输多个信号。 数据传输系统包括第一至第三传输线（311,313,315）并发送2位数据。 第一至第三传输线传送具有第一至第三电压电平之一的第一至第三电压信号中的每一个，使得第一和第二电场根据2位数据的逻辑状态具有不同的逻辑组合。 在第一和第二传输线之间产生第一电场。 在第二和第三传输线之间产生第二电场。 传动系统包括驱动单元（410）和接收单元（470）。 驱动单元响应于2位数据产生第一至第三电压信号，并将第一至第三电压信号发送到第一至第三传输线。 接收单元接收第一至第三电压信号并产生2位数据。
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公开(公告)号：KR100660873B1
公开(公告)日：2006-12-26
申请号：KR1020050066962
申请日：2005-07-22
Applicant: 삼성전자주식회사
Abstract: A memory system including an on-die termination having inductance is provided to keep stable gain characteristics against operation frequency variation by adding an inductor to an on-die termination part of a memory chip. In a memory chip(210), a first power supply line(202) is connected to a first power supply pad(211a,212,213). A second power supply line(204) is connected to a second power supply pad(211b). The memory chip also comprises at least one data input/output pad. A driver is connected to the first power supply line, and drives data with the data input/output pad. An on-die termination part is connected to the second power supply line, and has output characteristics matched to the impedance of a transmission line connected to the data input/output pad. The second power supply line is a power supply line dedicated to the on-die termination part.
Abstract translation: 提供包括具有电感的片上终端的存储器系统，以通过将电感器添加到存储器芯片的片上终端部分来针对工作频率变化保持稳定的增益特性。 在存储器芯片（210）中，第一电源线（202）连接到第一电源焊盘（211a，212,213）。 第二电源线（204）连接到第二电源焊盘（211b）。 存储器芯片还包括至少一个数据输入/输出焊盘。 驱动器连接到第一电源线，并用数据输入/输出板驱动数据。 芯片上终端部分连接到第二电源线，并且具有与连接到数据输入/输出焊盘的传输线的阻抗相匹配的输出特性。 第二电源线是专用于片上终端部件的电源线。
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公开(公告)号：KR100574951B1
公开(公告)日：2006-05-02
申请号：KR1020030076734
申请日：2003-10-31
Applicant: 삼성전자주식회사
IPC: H01L23/50
CPC classification number: G11C5/04
Abstract: 개선된 레지스터 배치 구조를 가지는 메모리 모듈이 개시된다. 본 발명의 실시예에 따른 메모리 모듈은, 앞면과 뒷면에 각각 메모리 칩들을 장착하는 메모리 모듈에 있어서 제 1 레지스터 쌍 및 제 2 레지스터 쌍을 구비한다. 제 1 레지스터 쌍은 상기 메모리 모듈의 중앙부에 배치되며 상기 메모리 모듈의 앞면과 뒷면의 서로 대응되는 위치에 배치된다. 제 2 레지스터 쌍은 상기 제 1 레지스터 쌍에 인접하여 배치되며 상기 메모리 모듈의 앞면과 뒷면의 서로 대응되는 위치에 배치된다. 상기 제 1 레지스터 쌍은 수신된 신호를 상기 제 2 레지스터 쌍으로 데이지 체인(Daisy-Chain) 방법을 이용하여 전송한다. 상기 제 1 레지스터 쌍 및 상기 제 2 레지스터 쌍은 높이 방향으로 서로 엇갈리게 배치된다. 상기 제 1 레지스터 쌍 및 상기 제 2 레지스터 쌍은 출력되는 하나의 신호는 상기 제 1 레지스터 쌍 또는 상기 제 2 레지스터 쌍의 좌측에 위치한 메모리 칩들로 인가되고 나머지 하나의 신호는 상기 제 1 레지스터 쌍 또는 상기 제 2 레지스터 쌍의 우측에 위치한 메모리 칩들로 인가된다. 본 발명에 따른 메모리 모듈은 레지스터들 사이의 신호 전송을 데이지 체인 방법을 이용하고 레지스터들을 서로 상하방향으로 엇갈리게 배치함으로써 신호 충실도를 향상시키고 메모리 모듈상의 공간을 확보할 수 있으며 따라서 메모리 칩의 추가 확장이 가능하여 더욱 고용량의 메모리 모듈 제공이 가능한 장점이 있다.
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公开(公告)号：KR100264128B1
公开(公告)日：2000-08-16
申请号：KR1019970033231
申请日：1997-07-16
Applicant: 삼성전자주식회사
IPC: F24C7/00
Abstract: PURPOSE: A method for designing a cooking chamber of a microwave oven is provided to optimize the shape of a cooking chamber for uniformly cooking foodstuff without real testing of cooking efficiency via a real microwave oven. CONSTITUTION: An optimal cooking chamber design method comprises the steps of: measuring distribution of electric fields of respective coordinates in a cooking chamber upon input of the initial shape of a cooking chamber and the electrical permittivity of foodstuff; dividing a variable range of the cooking chamber into zones of specific number, dividing the foodstuff into specific parts, and measuring energy absorbed in the foodstuff in the cooking chamber corresponding to the divided zones; outputting an objective function by operating the maximum and the minimum of the energy of each zone; detecting a variable by operating the minimum of the objective function; and indicating the variable on a display unit. Accordingly, a cooking chamber of optimal cooking efficiency is designed without real cooking via a microwave oven. Further, time and cost for development of a microwave oven are saved.
Abstract translation: 目的：提供一种用于设计微波炉烹饪室的方法，以优化用于均匀烹饪食物的烹饪室的形状，而无需通过真正的微波炉实际测量烹饪效率。 构成：最佳烹饪室设计方法包括以下步骤：在烹饪室的初始形状的输入和食品的电容率输入时，测量烹饪室中各坐标的电场分布; 将烹饪室的可变范围划分为特定数量的区域，将食物分成特定部分，并测量与分割区域对应的烹饪室中食物中吸收的能量; 通过操作每个区域的能量的最大和最小来输出目标函数; 通过操作目标函数的最小值来检测变量; 并在显示单元上指示变量。 因此，在没有通过微波炉进行真正烹饪的情况下设计具有最佳烹饪效率的烹饪室。 此外，节省了微波炉的开发的时间和成本。
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