公开(公告)号：KR1020050091575A

公开(公告)日：2005-09-15

申请号：KR1020040017063

申请日：2004-03-12

Applicant: 삼성전자주식회사

Inventor： 박봉태 ,  장성남

IPC: H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11536 ,  H01L27/11541

Abstract: 리세스된 비트라인들을 갖는 반도체 기억소자 및 그 제조방법을 제공한다. 이 소자는 반도체기판 상에 적층된 층간절연막을 구비한다. 상기 층간절연막 내에 그루브들이 제공된다. 상기 그루브들은 리세스된 비트라인들로 채워진다. 상기 리세스된 비트라인들은 상기 층간절연막의 상부면 보다 낮다. 상기 리세스된 비트라인들은 상기 그루브들을 채우는 초기 비트라인들을 형성한 후에 상기 초기 비트라인들을 선택적으로 부분식각 함으로써 형성된다.

公开(公告)号：KR1020040033774A

公开(公告)日：2004-04-28

申请号：KR1020020063026

申请日：2002-10-16

Applicant: 삼성전자주식회사

Inventor： 정연운 ,  박봉태

IPC: H01L27/115

Abstract: PURPOSE: An electrical connection line of a flash memory device and a manufacturing method thereof are provided to be capable of simply and easily forming a butting contact. CONSTITUTION: An electrical connection line of a flash memory device is provided with a semiconductor substrate, a plurality of lines formed on the semiconductor substrate, and a common source line(110) electrically connected to the semiconductor substrate between the lines. At this time, the line is completed by sequentially forming a gate dielectric layer(101), a floating gate(102), an interlayer dielectric(103), and a control gate(104,105). The electrical connection line further includes a butting contact(210) for electrically connecting the control gate with the floating gate and a bit line electrically connected to the common source line or the butting contact.

Abstract translation: 目的：提供闪存器件的电连接线及其制造方法，以便简单且容易地形成对接触点。 构成：闪速存储器件的电连接线设置有半导体衬底，形成在半导体衬底上的多条线，以及在线之间电连接到半导体衬底的公共源极线（110）。 此时，通过顺序地形成栅极电介质层（101），浮动栅极（102），层间电介质（103）和控制栅极（104,105）来完成线。 电连接线还包括用于将控制栅极与浮动栅极电连接的对接触点（210）和电连接到公共源极线或对接触点的位线。

公开(公告)号：KR102059183B1

公开(公告)日：2019-12-24

申请号：KR1020130024622

申请日：2013-03-07

Applicant: 삼성전자주식회사

Inventor： 유장현 ,  박형 ,  박봉태 ,  한지훈

IPC: H01L27/115 ,  H01L21/8247

公开(公告)号：KR100830579B1

公开(公告)日：2008-05-21

申请号：KR1020060101966

申请日：2006-10-19

Applicant: 삼성전자주식회사

Inventor： 박봉태 ,  최정혁

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: 비휘발성 메모리 장치 및 그 형성 방법이 제공된다. 상기 비휘발성 메모리 장치는 반도체 기판에 배치되어 활성 영역들을 한정하는 소자 분리막, 상기 활성 영역들 상에 배치된 부유 게이트들, 상기 부유 게이트들 상에 배치되는 워드 라인을 포함하며, 상기 소자 분리막은 그 상부에서 상기 부유 게이트들과 이격되어 배치되는 오목 영역을 갖고, 상기 워드 라인은 상기 오목 영역에 삽입되는 돌출부를 갖는다.
비휘발성, 부유 게이트용 패턴, 소자 분리막

公开(公告)号：KR1020060039296A

公开(公告)日：2006-05-08

申请号：KR1020040088433

申请日：2004-11-02

Applicant: 삼성전자주식회사

Inventor： 박봉태 ,  장성남

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/76897 ,  H01L21/823475

Abstract: 저항 패턴을 갖는 비휘발성 기억 소자 및 그 형성 방법을 제공한다. 이 소자는 기판에 형성된 소자분리막 상에 배치된 저항 패턴 및 상기 저항 패턴을 덮는 층간 절연막을 포함한다. 제1 및 제2 플러그들이 층간 절연막을 관통하여 저항 패턴의 상부면의 양 가장자리를 각각 노출시키는 제1 및 제2 콘택홀들을 각각 채운다. 제1 및 제2 배선들이 층간 절연막 상에 배치되어 제1 및 제2 플러그들과 각각 접속한다. 복수개의 더미 플러그들이 층간 절연막을 관통하여 제1 플러그와 제2 플러그 사이의 저항 패턴의 상부면을 노출시키는 복수개의 더미 콘택홀들을 각각 채운다.

公开(公告)号：KR1020040063350A

公开(公告)日：2004-07-14

申请号：KR1020030000737

申请日：2003-01-07

Applicant: 삼성전자주식회사

Inventor： 정연운 ,  박봉태

IPC: H01L27/115

Abstract: PURPOSE: A NAND-type flash memory device is provided to improve an insulation effect between a bitline and a common source line, and to facilitate a subsequent process by decreasing the whole height of an insulation layer. CONSTITUTION: A semiconductor substrate(100) is prepared. A string(110) includes a string select line(300), a wordline(200) and a ground select line(400) that extend in the same direction on the substrate and are disposed in parallel. A bitline(700) extends in a direction substantially perpendicular to the extension direction of each line of the string. A contact plug is electrically connected to a drain(120) of the string select line and the bitline. A common source line(500) includes a lower layer(510) and an upper layer(520) wherein the lower layer is electrically connected to a source(140) of the ground select line and an upper layer is electrically insulated from the bitline.

Abstract translation: 目的：提供NAND型闪速存储器件以改善位线和公共源极线之间的绝缘效应，并且通过降低绝缘层的整个高度来促进随后的工艺。 构成：制备半导体衬底（100）。 串（110）包括串联选择线（300），字线（200）和接地选择线（400），其在基板上沿相同的方向延伸并且平行设置。 位线（700）在与弦线的每条线的延伸方向基本垂直的方向上延伸。 接触插塞电连接到串选择线和位线的漏极（120）。 公共源线（500）包括下层（510）和上层（520），其中下层电连接到地选线的源极（140），并且上层与位线电绝缘。

公开(公告)号：KR1020040016504A

公开(公告)日：2004-02-25

申请号：KR1020020048709

申请日：2002-08-17

Applicant: 삼성전자주식회사

Inventor： 조상연 ,  신광식 ,  박봉태

IPC: H01L27/115

Abstract: PURPOSE: A method for fabricating a self-aligned common source line of a NAND-type flash memory device is provided to effectively reduce the chip area of the device by minimizing a process margin between ground select lines adjacent to the common source line. CONSTITUTION: When a gate line is formed on a semiconductor substrate(100) by a photolithography process, an extended pattern is formed altogether with the gate line. The extended pattern is patterned to form an opening exposing a portion between the extended patterns of the semiconductor substrate. The extended pattern is separated to form two adjacent ground select lines(371). A spacer is formed to cover the inner wall of the opening. The opening is filled with the common source line(500) that is electrically separated from the ground select line by the spacer.

Abstract translation: 目的：提供一种用于制造NAND型闪速存储器件的自对准公共源极线的方法，以通过最小化与公共源极线相邻的接地选择线之间的工艺裕度来有效地减小器件的芯片面积。 构成：当通过光刻工艺在半导体衬底（100）上形成栅极线时，与栅极线一起形成延伸图案。 图案化延伸图案以形成露出半导体衬底的延伸图案之间的部分的开口。 扩展图案被分离以形成两个相邻的地选线（371）。 形成间隔件以覆盖开口的内壁。 该开口填充有通过间隔件与地选择线电分离的公共源极线（500）。

公开(公告)号：KR1020030073937A

公开(公告)日：2003-09-19

申请号：KR1020020013723

申请日：2002-03-14

Applicant: 삼성전자주식회사

Inventor： 박봉태 ,  조상연 ,  정연운

IPC: H01L21/8247

Abstract: PURPOSE: A method for fabricating a floating gate type non-volatile memory(NVM) device is provided to reduce an operating voltage by increasing the surface area of a floating gate electrode so that the capacitance of the floating gate electrode and a control gate electrode is increased. CONSTITUTION: An active region for forming an isolation layer(102) is defined in a predetermined region of a semiconductor substrate(101). A tunnel oxide layer(103) is formed on the active region. A floating gate pattern(104b) is formed on the tunnel oxide layer, having a cross section of a U type and exposing the isolation layer. A gate interlayer dielectric and a control gate layer are sequentially formed on the entire surface of the semiconductor substrate including the floating gate pattern. The control gate layer, the gate interlayer dielectric and the floating gate pattern are consecutively patterned to form the control gate electrode crossing the upper portion of the active region and the floating gate electrode interposed between the control gate electrode and the active region.

Abstract translation: 目的：提供一种用于制造浮动栅型非易失性存储器（NVM）器件的方法，通过增加浮栅电极的表面积来降低工作电压，使得浮栅电极和控制栅电极的电容为 增加。 构成：用于形成隔离层（102）的有源区限定在半导体衬底（101）的预定区域中。 隧道氧化物层（103）形成在有源区上。 在隧道氧化物层上形成浮栅图案（104b），其具有U型横截面并暴露隔离层。 在包括浮置栅极图案的半导体衬底的整个表面上依次形成栅极层间电介质和控制栅极层。 控制栅极层，栅极层间电介质和浮置栅极图案被连续地图案化以形成跨越有源区的上部的跨越控制栅电极和插在控制栅电极和有源区之间的浮栅。

公开(公告)号：KR1020020062435A

公开(公告)日：2002-07-26

申请号：KR1020010003430

申请日：2001-01-20

Applicant: 삼성전자주식회사

Inventor： 박봉태

IPC: H01L27/115

Abstract: PURPOSE: A flash memory device is provided to simplify a fabricating process and to stabilize a process for forming a bitline contact hole, by forming a bitline plug and a common source line in the same step. CONSTITUTION: A plurality of cell strings are formed on a semiconductor substrate. The common source line(27) is commonly connected to a source region(25) of the plurality of cell strings. The bitline plug(28) is formed in a drain region(24) of the respective cell strings. The first conductive layer pattern(30) is disconnected on the common source line, connected to the bitline plug and crossing the common source line. The second conductive layer pattern(33) connects the first conductive layer patterns at both sides of the common source line over the common source line. The first and second conductive layer patterns constitutes a bitline(34).

Abstract translation: 目的：通过在同一步骤中形成位线插头和公共源极线，提供闪存器件以简化制造工艺并稳定形成位线接触孔的工艺。 构成：在半导体衬底上形成多个电池串。 公共源极线（27）通常连接到多个单元串的源极区域（25）。 位线插头（28）形成在各个电池串的漏区（24）中。 第一导电层图案（30）在公共源极线上断开，连接到位线插头并且穿过公共源极线。 第二导电层图案（33）在公共源极线上连接公共源极线的两侧的第一导电层图案。 第一和第二导电层图案构成位线（34）。

公开(公告)号：KR1020020013193A

公开(公告)日：2002-02-20

申请号：KR1020000046674

申请日：2000-08-11

Applicant: 삼성전자주식회사

Inventor： 장성남 ,  황덕성 ,  정연운 ,  박봉태

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/8247

Abstract: PURPOSE: A method for forming a common source line of a flash memory device is provided to easily form or fill a bit line contact hole and to reduce damage to an insulation between bit line contact plugs or a bit line and the common source line, by forming the common source line have the same height as the gate line. CONSTITUTION: A source line trench is formed in the common source line region in the course of forming an isolation trench on a silicon substrate(10). An ion implantation process is performed regarding the silicon substrate constituting the bottom surface of the source line trench. A floating gate layer(63',73) is stacked and patterned to form a floating gate string pattern, wherein the source line trench is filled in the floating gate layer to form the common source line.

Abstract translation: 目的：提供一种用于形成闪存器件的公共源极线的方法，以容易地形成或填充位线接触孔，并且通过以下方式减少对位线接触插塞或位线与公共源极线之间的绝缘的损坏，由 形成公共源极线具有与栅极线相同的高度。 构成：在硅衬底（10）上形成隔离沟槽的过程中，在公共源极线区域中形成源极线沟槽。 对构成源极线沟槽的底面的硅衬底进行离子注入工艺。 堆叠并图案化浮栅层（63'，73）以形成浮栅阵列图案，其中源极线沟槽填充在浮栅层中以形成公共源极线。