公开(公告)号：KR1020050074850A

公开(公告)日：2005-07-19

申请号：KR1020040002761

申请日：2004-01-14

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  이정형 ,  원석준 ,  권대진 ,  김원홍 ,  송민우

IPC: H01L27/108

CPC classification number: H01L21/02172 ,  H01G4/10 ,  H01G4/20 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31645 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/65

Abstract: In a capacitor, and a method of fabricating the same, the capacitor includes a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer, wherein the dielectric layer includes a lower dielectric region contacting the lower electrode, an upper dielectric region contacting the upper electrode, and at least one middle dielectric region between the lower dielectric region and the upper dielectric region, the at least one middle dielectric region having a less crystalline region than both the lower dielectric region and the upper dielectric region.

公开(公告)号：KR100493040B1

公开(公告)日：2005-06-07

申请号：KR1020020087241

申请日：2002-12-30

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  윤명근 ,  정용국 ,  권대진

IPC: H01L21/8242

CPC classification number: H01L21/022 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L28/65

Abstract: 산화 알루미늄막/고유전체막/산화 알루미늄막으로 구성된 유전막을 포함하는 반도체 소자의 커패시터 및 그 제조방법에 대하여 개시한다. 본 발명에 의한 반도체 소자의 커패시터는 반도체 기판에 형성된 커패시터 하부 전극과 커패시터 하부 전극 상에 산화 알루미늄으로 형성된 제1 유전막, 제1 유전막 상에 산화 알루미늄보다 유전 상수가 큰 물질로 형성된 제2 유전막 및 제2 유전막 상에 산화 알루미늄으로 형성된 제3 유전막으로 구성된 유전막과 이 유전막 상에 형성된 커패시터 상부 전극을 포함한다. 본 발명에 의한 커패시터는 전력의 소모가 적고 고집적화에 유리하도록 단위 면적당 높은 커패시턴스를 갖는 등 여러 가지 전기적 특성이 우수하다.

公开(公告)号：KR1020050040464A

公开(公告)日：2005-05-03

申请号：KR1020030075670

申请日：2003-10-28

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  정용국 ,  권대진 ,  송민우 ,  김원홍

IPC: H01L27/10

CPC classification number: H01L28/91 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/0805

Abstract: 수직으로 연장된 배선간 엠아이엠 커패시터를 갖는 로직소자 및 그것을 제조하는 방법이 개시된다. 상기 로직소자는 반도체 기판을 포함한다. 상기 반도체 기판 상부에 하부배선이 위치하고, 상기 하부배선 상부에 상부배선이 위치한다. 상기 하부배선과 상기 상부배선 사이에 U자형(U-shaped) 하부 금속플레이트가 개재된다. 상기 U자형 하부 금속플레이트는 상기 하부배선에 직접 접한다. 커패시터 유전막이 상기 하부 금속플레이트의 내면(inner surface)을 덮는다. 또한, 상기 커패시터 유전막은 상기 하부 금속플레이트의 가장자리(brim)와 상기 상부배선 사이에 개재된 연장부를 갖는다. 한편, 상부 금속플레이트가 상기 커패시터 유전막의 내면을 덮는다. 상기 상부 금속플레이트는 상기 상부배선에 직접 접하고, 상기 커패시터 유전막에 의해 한정된다.

公开(公告)号：KR1020050033323A

公开(公告)日：2005-04-12

申请号：KR1020030069315

申请日：2003-10-06

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  정용국 ,  송민우

IPC: H01L21/316

Abstract: A method for fabricating a hafnium oxide film is provided to obtain an improved leakage current characteristic and a higher permittivity than a conventional permittivity by forming a high permittivity layer of hafnium floating state and a leakage current suppression layer. A crystallized high permittivity layer of hafnium floating state (HfxOy;Y=1,X>0.5) is formed on a semiconductor substrate. A leakage current suppression layer oriented along a crystal structure of the high permittivity layer is formed on the crystallized high permittivity layer. The high permittivity layer has a permittivity of 25 to 120. The high permittivity layer having a thickness of 300Å to 1000Å is formed using CVD(chemical vapor deposition) method.

Abstract translation: 提供一种制造氧化铪膜的方法，通过形成铪浮动状态的高介电常数层和泄漏电流抑制层，获得比常规介电常数更高的漏电流特性和更高的介电常数。 在半导体衬底上形成铪浮态（Hf x O y; Y = 1，X> 0.5）的结晶高介电常数层。 在结晶化高电容率层上形成沿着高电容率层的晶体结构取向的漏电流抑制层。 高电容率层的介电常数为25〜120。使用CVD（化学气相沉积）法形成厚度为300至1000的高介电常数层。

公开(公告)号：KR1020050028748A

公开(公告)日：2005-03-23

申请号：KR1020030065272

申请日：2003-09-19

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  원석준 ,  권대진 ,  김원홍

IPC: H01L27/02

CPC classification number: H01L28/40 ,  H01L21/31637 ,  H01L21/31645

Abstract: An analog capacitor having at least 3 high-k dielectric layers is provided to optimize a voltage coefficient of capacitance and a leakage current characteristic while having a high-k dielectric layer by making high-k dielectric layer with an excellent voltage coefficient of capacitance come in contact with plates and by interposing a high-k dielectric layer capable of preventing a leakage current between the high-k dielectric layers. A lower plate(11) is formed. An upper plate(15) corresponding to the lower plate is formed. At least three high-k dielectric layers(13) are interposed between the lower and upper plates, including a bottom dielectric layer(13a) in contact with the lower plate, a top dielectric layer(13c) in contact with the upper plate, and a middle dielectric layer(13b) interposed between the bottom and top dielectric layers. Each of bottom and top dielectric layers is a high dielectric layer having a small absolute value of the coefficient of a quadratic term of a voltage coefficient as compared with the middle dielectric layer. The middle dielectric layer is a high dielectric layer having a small leakage current as compared with the bottom and top dielectric layers, respectively.

Abstract translation: 提供具有至少3个高k电介质层的模拟电容器，以通过使具有优异的电容电压系数的高k电介质层进入而具有高k电介质层，从而优化电容的电压系数和漏电流特性 通过插入能够防止高k电介质层之间的漏电流的高k电介质层与板接触。 形成下板（11）。 形成对应于下板的上板（15）。 至少三个高k电介质层（13）插入在下板和上板之间，包括与下板接触的底电介质层（13a），与上板接触的顶介电层（13c），以及 插入在所述底部和顶部电介质层之间的中间介电层（13b）。 底部和顶部电介质层是与中间介电层相比具有电压系数的二次项的系数的绝对值小的高介电层。 中间介电层是分别与底部和顶部电介质层相比具有小的漏电流的高电介质层。

公开(公告)号：KR1020030046902A

公开(公告)日：2003-06-18

申请号：KR1020010077228

申请日：2001-12-07

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  정용국

IPC: H01L27/108

Abstract: PURPOSE: A semiconductor capacitor having bottom plate electrode and fabrication method thereof are provided to form a storage electrode of cylinder or stack type instead of a conventional method of exposing a bottom electrode using wet solution. CONSTITUTION: The first interlayer dielectric(205) having a conductive plug(210) is formed on a semiconductor substrate(200). A storage electrode(240) having cylindrical outside and inside parts is formed on the conductive plug. A dielectric layer(235) and plate electrode(230) are formed on the outside part of the storage electrode. A supporting layer beneath a bottom plate electrode(220) is formed to prevent short between the bottom plate electrode and the conductive plug.

Abstract translation: 目的：提供具有底板电极的半导体电容器及其制造方法，以形成圆柱体或堆叠型存储电极，而不是使用湿溶液暴露底部电极的常规方法。 构成：在半导体衬底（200）上形成具有导电插塞（210）的第一层间电介质（205）。 在导电插头上形成具有圆筒形外部和内部的存储电极（240）。 在存储电极的外侧部分上形成电介质层（235）和平板电极（230）。 形成底板电极（220）下方的支撑层，以防止底板电极和导电插塞之间的短路。

公开(公告)号：KR1020130125583A

公开(公告)日：2013-11-19

申请号：KR1020120049216

申请日：2012-05-09

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  채승호 ,  허정식

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66477 ,  H01L29/6656 ,  H01L29/6659 ,  H01L21/0234

Abstract: The present invention provides a semiconductor device and a method manufacturing the same. The semiconductor device includes a first insulator film arranged on a substrate; a gate electrode arranged on the first insulator film; and a second insulator film including a first discharge site and arranged on the gate electrode and the first insulator film.

Abstract translation: 本发明提供一种半导体器件及其制造方法。 半导体器件包括布置在衬底上的第一绝缘膜; 布置在所述第一绝缘膜上的栅电极; 以及包括第一放电位置并且布置在栅电极和第一绝缘膜上的第二绝缘膜。

公开(公告)号：KR1020130092215A

公开(公告)日：2013-08-20

申请号：KR1020120013807

申请日：2012-02-10

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  박상욱 ,  최민희

IPC: H01L21/318 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/78

CPC classification number: H01L29/7831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823807 ,  H01L21/8258 ,  H01L23/291 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor device is provided to prevent foreign materials like ions from being diffused into a gate insulating layer by forming a nitride layer on a gate including a high density thin film. CONSTITUTION: A gate structure (110) includes a gate insulating layer and a gate electrode layer. A first nitride layer (120) is formed on a substrate and the gate structure. The first nitride layer includes silicon. A second nitride layer (130) is formed on the first nitride layer. The silicon atom fraction of the second nitride layer is lower than the silicon atom fraction of the first nitride layer.

Abstract translation: 目的：提供一种半导体器件，以通过在包括高密度薄膜的栅极上形成氮化物层来防止诸如离子的异物扩散到栅极绝缘层中。 构成：栅极结构（110）包括栅极绝缘层和栅极电极层。 在衬底和栅极结构上形成第一氮化物层（120）。 第一氮化物层包括硅。 在第一氮化物层上形成第二氮化物层（130）。 第二氮化物层的硅原子分数低于第一氮化物层的硅原子分数。

公开(公告)号：KR1020110135771A

公开(公告)日：2011-12-19

申请号：KR1020100055691

申请日：2010-06-11

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  신동석 ,  김종훈 ,  유현관 ,  김기은

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843 ,  H01L21/32051

Abstract: PURPOSE: A method for manufacturing a semiconductor integrated circuit device is provided to prevent the shape deformation of a silicide layer by forming a stress buffer layer and a stress layer. CONSTITUTION: A gate pattern and a spacer are formed on a semiconductor substrate. The gate pattern comprises a gate insulating layer and a gate electrode. The spacer is arranged in the side wall of the gate pattern. A silicide layer(162) is formed on the semiconductor substrate which is revealed by the gate pattern and the spacer in a silicide process. A stress buffer layer(170) is formed on a product in which the silicide layer is formed. A stress layer(180) is formed on the stress buffer layer. The stress layer is a tension stress layer and the stress buffer layer is a compression stress layer.

Abstract translation: 目的：提供一种制造半导体集成电路器件的方法，以通过形成应力缓冲层和应力层来防止硅化物层的形状变形。 构成：在半导体衬底上形成栅极图案和间隔物。 栅极图案包括栅极绝缘层和栅电极。 间隔件布置在栅极图案的侧壁中。 在半导体衬底上形成硅化物层（162），其通过栅极图案和间隔物在硅化处理中显露。 在其上形成硅化物层的产品上形成应力缓冲层（170）。 应力层（180）形成在应力缓冲层上。 应力层是张力应力层，应力缓冲层是压应力层。

公开(公告)号：KR1020070076721A

公开(公告)日：2007-07-25

申请号：KR1020060005934

申请日：2006-01-19

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  신동석

IPC: H01L21/20

CPC classification number: H01L21/67017 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/02334 ,  H01L21/0234

Abstract: A method for improving a thin film forming process of a wafer is provided to uniformly control a thickness of a thin film to be formed on a wafer by consistently maintaining an internal environment in the chamber. An inside of a chamber of a semiconductor fabricating apparatus is primarily cleaned(S100) by NF3 of 2000 to 5000 sccm, in which a wafer is not introduced in the chamber. After a thin film is formed on the inside of the chamber(S200), the inside of the chamber with the thin film is secondarily cleaned(S210). After the wafer is introduced into the chamber(S300) to form a thin film on the wafer, the wafer is withdrawn from the chamber, and the chamber is thirdly cleaned(S310).

Abstract translation: 提供一种用于改善晶片的薄膜形成工艺的方法，以通过始终保持室内的内部环境来均匀地控制待形成在薄片上的薄膜的厚度。 半导体制造装置的室内部通过2000〜5000sccm的NF3主要被清洗（S100），其中晶片未被引入室内。 在室内部形成薄膜（S200）之后，再次清洗具有薄膜的室内（S210）。 在晶片被引入腔室（S300）中以在晶片上形成薄膜之后，将晶片从腔室中取出，并且将腔室第三次清洁（S310）。